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[RISCV] Move Pre-RA pseudo expansion from addMachineSSAOptimization to addPreRegAlloc. 

addMachineSSAOptimization is skipped for -O0, but this pass is
required for -O0.
This commit is contained in:
Craig Topper 2022-08-01 13:42:01 -07:00
parent 5ef987c985
commit e07a8155f5
2 changed files with 2 additions and 1 deletions
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2
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
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@ -254,10 +254,10 @@ void RISCVPassConfig::addMachineSSAOptimization() {
if (TM->getTargetTriple().getArch() == Triple::riscv64)
addPass(createRISCVSExtWRemovalPass());
addPass(createRISCVPreRAExpandPseudoPass());
}
void RISCVPassConfig::addPreRegAlloc() {
addPass(createRISCVPreRAExpandPseudoPass());
if (TM->getOptLevel() != CodeGenOpt::None)
addPass(createRISCVMergeBaseOffsetOptPass());
addPass(createRISCVInsertVSETVLIPass());

1
llvm/test/CodeGen/RISCV/O0-pipeline.ll
View File

@ -35,6 +35,7 @@
; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection
; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
; CHECK-NEXT: Local Stack Slot Allocation
; CHECK-NEXT: RISCV Pre-RA pseudo instruction expansion pass
; CHECK-NEXT: RISCV Insert VSETVLI pass
; CHECK-NEXT: Eliminate PHI nodes for register allocation
; CHECK-NEXT: Two-Address instruction pass