[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. AArch64 edition

llvm-svn: 207510

llvm/lib/Target/AArch64/AArch64AsmPrinter.h

@@ -45,15 +45,15 @@ class LLVM_LIBRARY_VISIBILITY AArch64AsmPrinter : public AsmPrinter {
   MCOperand lowerSymbolOperand(const MachineOperand &MO,
                                const MCSymbol *Sym) const;
 
-  void EmitInstruction(const MachineInstr *MI);
+  void EmitInstruction(const MachineInstr *MI) override;
-  void EmitEndOfAsmFile(Module &M);
+  void EmitEndOfAsmFile(Module &M) override;
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                        unsigned AsmVariant, const char *ExtraCode,
-                       raw_ostream &O);
+                       raw_ostream &O) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              unsigned AsmVariant, const char *ExtraCode,
-                             raw_ostream &O);
+                             raw_ostream &O) override;
 
   /// printSymbolicAddress - Given some kind of reasonably bare symbolic
   /// reference, print out the appropriate asm string to represent it. If
@@ -65,11 +65,11 @@ class LLVM_LIBRARY_VISIBILITY AArch64AsmPrinter : public AsmPrinter {
                             bool PrintImmediatePrefix,
                             StringRef Suffix, raw_ostream &O);
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "AArch64 Assembly Printer";
   }
 
-  virtual bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 };
 } // end namespace llvm
 

llvm/lib/Target/AArch64/AArch64BranchFixupPass.cpp

@@ -136,9 +136,9 @@ namespace {
     static char ID;
     AArch64BranchFixup() : MachineFunctionPass(ID) {}
 
-    virtual bool runOnMachineFunction(MachineFunction &MF);
+    bool runOnMachineFunction(MachineFunction &MF) override;
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "AArch64 branch fixup pass";
     }
 

llvm/lib/Target/AArch64/AArch64FrameLowering.h

@@ -47,8 +47,8 @@ public:
 
   /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
   /// the function.
-  virtual void emitPrologue(MachineFunction &MF) const;
+  void emitPrologue(MachineFunction &MF) const override;
-  virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 
   /// Decides how much stack adjustment to perform in each phase of the prologue
   /// and epilogue.
@@ -59,21 +59,21 @@ public:
                                      unsigned &FrameReg, int SPAdj,
                                      bool IsCalleeSaveOp) const;
 
-  virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
+  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
-                                                    RegScavenger *RS) const;
+                                            RegScavenger *RS) const override;
 
-  virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
+  bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
+                                MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                const std::vector<CalleeSavedInfo> &CSI,
-                                        const TargetRegisterInfo *TRI) const;
+                                const TargetRegisterInfo *TRI) const override;
-  virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
+  bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
+                                MachineBasicBlock::iterator MI,
-                                        const std::vector<CalleeSavedInfo> &CSI,
+                                const std::vector<CalleeSavedInfo> &CSI,
-                                        const TargetRegisterInfo *TRI) const;
+                                const TargetRegisterInfo *TRI) const override;
 
-  void eliminateCallFramePseudoInstr(MachineFunction &MF,
+  void
-                                     MachineBasicBlock &MBB,
+  eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MI) const;
+                                MachineBasicBlock::iterator MI) const override;
 
   /// If the register is X30 (i.e. LR) and the return address is used in the
   /// function then the callee-save store doesn't actually kill the register,
@@ -94,12 +94,12 @@ public:
                        unsigned NumClasses) const;
 
 
-  virtual bool hasFP(const MachineFunction &MF) const;
+  bool hasFP(const MachineFunction &MF) const override;
 
-  virtual bool useFPForAddressing(const MachineFunction &MF) const;
+  bool useFPForAddressing(const MachineFunction &MF) const;
 
   /// On AA
-  virtual bool hasReservedCallFrame(const MachineFunction &MF) const;
+  bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
 };
 

llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -46,7 +46,7 @@ public:
       Subtarget(&TM.getSubtarget<AArch64Subtarget>()) {
   }
 
-  virtual const char *getPassName() const {
+  const char *getPassName() const override {
     return "AArch64 Instruction Selection";
   }
 
@@ -86,7 +86,7 @@ public:
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                     char ConstraintCode,
-                                    std::vector<SDValue> &OutOps);
+                                    std::vector<SDValue> &OutOps) override;
 
   bool SelectLogicalImm(SDValue N, SDValue &Imm);
 
@@ -108,7 +108,7 @@ public:
   SDNode *LowerToFPLitPool(SDNode *Node);
   SDNode *SelectToLitPool(SDNode *N);
 
-  SDNode* Select(SDNode*);
+  SDNode* Select(SDNode*) override;
 private:
   /// Get the opcode for table lookup instruction
   unsigned getTBLOpc(bool IsExt, bool Is64Bit, unsigned NumOfVec);

llvm/lib/Target/AArch64/AArch64ISelLowering.h

@@ -205,7 +205,7 @@ class AArch64TargetLowering : public TargetLowering {
 public:
   explicit AArch64TargetLowering(AArch64TargetMachine &TM);
 
-  const char *getTargetNodeName(unsigned Opcode) const;
+  const char *getTargetNodeName(unsigned Opcode) const override;
 
   CCAssignFn *CCAssignFnForNode(CallingConv::ID CC) const;
 
@@ -213,18 +213,18 @@ public:
                                CallingConv::ID CallConv, bool isVarArg,
                                const SmallVectorImpl<ISD::InputArg> &Ins,
                                SDLoc dl, SelectionDAG &DAG,
-                               SmallVectorImpl<SDValue> &InVals) const;
+                               SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerReturn(SDValue Chain,
                       CallingConv::ID CallConv, bool isVarArg,
                       const SmallVectorImpl<ISD::OutputArg> &Outs,
                       const SmallVectorImpl<SDValue> &OutVals,
-                      SDLoc dl, SelectionDAG &DAG) const;
+                      SDLoc dl, SelectionDAG &DAG) const override;
 
-  virtual unsigned getByValTypeAlignment(Type *Ty) const override;
+  unsigned getByValTypeAlignment(Type *Ty) const override;
 
   SDValue LowerCall(CallLoweringInfo &CLI,
-                    SmallVectorImpl<SDValue> &InVals) const;
+                    SmallVectorImpl<SDValue> &InVals) const override;
 
   SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
                           CallingConv::ID CallConv, bool IsVarArg,
@@ -268,15 +268,15 @@ public:
   SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
                               MachineFrameInfo *MFI, int ClobberedFI) const;
 
-  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
+  EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
 
   bool DoesCalleeRestoreStack(CallingConv::ID CallCC, bool TailCallOpt) const;
 
   bool IsTailCallConvention(CallingConv::ID CallCC) const;
 
-  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
-  bool isLegalICmpImmediate(int64_t Val) const;
+  bool isLegalICmpImmediate(int64_t Val) const override;
 
   /// \brief Return true if the addressing mode represented by AM is legal for
   /// this target, for a load/store of the specified type.
@@ -299,8 +299,9 @@ public:
   SDValue getSelectableIntSetCC(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                          SDValue &A64cc, SelectionDAG &DAG, SDLoc &dl) const;
 
-  virtual MachineBasicBlock *
+  MachineBasicBlock *
-  EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
+  EmitInstrWithCustomInserter(MachineInstr *MI,
+                              MachineBasicBlock *MBB) const override;
 
   MachineBasicBlock *
   emitAtomicBinary(MachineInstr *MI, MachineBasicBlock *MBB,
@@ -347,34 +348,37 @@ public:
   SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 
-  virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
+  SDValue PerformDAGCombine(SDNode *N,DAGCombinerInfo &DCI) const override;
 
   /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
   /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
   /// expanded to FMAs when this method returns true, otherwise fmuladd is
   /// expanded to fmul + fadd.
-  virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
+  bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
 
   /// allowsUnalignedMemoryAccesses - Returns true if the target allows
   /// unaligned memory accesses of the specified type. Returns whether it
   /// is "fast" by reference in the second argument.
-  virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
+  bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
-                                             bool *Fast) const;
+                                     bool *Fast) const override;
 
-  ConstraintType getConstraintType(const std::string &Constraint) const;
+  ConstraintType
+  getConstraintType(const std::string &Constraint) const override;
 
-  ConstraintWeight getSingleConstraintMatchWeight(AsmOperandInfo &Info,
+  ConstraintWeight
-                                                  const char *Constraint) const;
+  getSingleConstraintMatchWeight(AsmOperandInfo &Info,
+                                 const char *Constraint) const override;
   void LowerAsmOperandForConstraint(SDValue Op,
                                     std::string &Constraint,
                                     std::vector<SDValue> &Ops,
-                                    SelectionDAG &DAG) const;
+                                    SelectionDAG &DAG) const override;
 
   std::pair<unsigned, const TargetRegisterClass*>
-  getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
+  getRegForInlineAsmConstraint(const std::string &Constraint,
+                               MVT VT) const override;
 
-  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
+  bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
-                                  unsigned Intrinsic) const override;
+                          unsigned Intrinsic) const override;
 
   /// getMaximalGlobalOffset - Returns the maximal possible offset which can
   /// be used for loads / stores from the global.
@@ -382,7 +386,7 @@ public:
 
 protected:
   std::pair<const TargetRegisterClass*, uint8_t>
-  findRepresentativeClass(MVT VT) const;
+  findRepresentativeClass(MVT VT) const override;
 
 private:
   const InstrItineraryData *Itins;

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -867,7 +867,7 @@ namespace {
     static char ID;
     LDTLSCleanup() : MachineFunctionPass(ID) {}
 
-    virtual bool runOnMachineFunction(MachineFunction &MF) {
+    bool runOnMachineFunction(MachineFunction &MF) override {
       AArch64MachineFunctionInfo* MFI
         = MF.getInfo<AArch64MachineFunctionInfo>();
       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
@@ -962,11 +962,11 @@ namespace {
       return Copy;
     }
 
-    virtual const char *getPassName() const {
+    const char *getPassName() const override {
       return "Local Dynamic TLS Access Clean-up";
     }
 
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+    void getAnalysisUsage(AnalysisUsage &AU) const override {
       AU.setPreservesCFG();
       AU.addRequired<MachineDominatorTree>();
       MachineFunctionPass::getAnalysisUsage(AU);

llvm/lib/Target/AArch64/AArch64InstrInfo.h

@@ -41,7 +41,7 @@ public:
   void copyPhysReg(MachineBasicBlock &MBB,
                    MachineBasicBlock::iterator I, DebugLoc DL,
                    unsigned DestReg, unsigned SrcReg,
-                   bool KillSrc) const;
+                   bool KillSrc) const override;
   void CopyPhysRegTuple(MachineBasicBlock &MBB,
                         MachineBasicBlock::iterator I, DebugLoc DL,
                         unsigned DestReg, unsigned SrcReg) const;
@@ -50,25 +50,26 @@ public:
                            MachineBasicBlock::iterator MI,
                            unsigned SrcReg, bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
-                           const TargetRegisterInfo *TRI) const;
+                           const TargetRegisterInfo *TRI) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MBBI,
                             unsigned DestReg, int FrameIdx,
                             const TargetRegisterClass *RC,
-                            const TargetRegisterInfo *TRI) const;
+                            const TargetRegisterInfo *TRI) const override;
 
   bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
-                     bool AllowModify = false) const;
+                     bool AllowModify = false) const override;
   unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
                         MachineBasicBlock *FBB,
                         const SmallVectorImpl<MachineOperand> &Cond,
-                        DebugLoc DL) const;
+                        DebugLoc DL) const override;
-  unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+  unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
-  bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
+  bool
+  ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
 
-  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
   /// Look through the instructions in this function and work out the largest
   /// the stack frame can be while maintaining the ability to address local

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

@@ -27,10 +27,11 @@ class AArch64Subtarget;
 struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
   AArch64RegisterInfo();
 
-  const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF =nullptr) const;
+  const MCPhysReg *
-  const uint32_t *getCallPreservedMask(CallingConv::ID) const;
+  getCalleeSavedRegs(const MachineFunction *MF =nullptr) const override;
+  const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
 
-  unsigned getCSRFirstUseCost() const {
+  unsigned getCSRFirstUseCost() const override {
     // The cost will be compared against BlockFrequency where entry has the
     // value of 1 << 14. A value of 5 will choose to spill or split really
     // cold path instead of using a callee-saved register.
@@ -39,38 +40,38 @@ struct AArch64RegisterInfo : public AArch64GenRegisterInfo {
 
   const uint32_t *getTLSDescCallPreservedMask() const;
 
-  BitVector getReservedRegs(const MachineFunction &MF) const;
+  BitVector getReservedRegs(const MachineFunction &MF) const override;
-  unsigned getFrameRegister(const MachineFunction &MF) const;
+  unsigned getFrameRegister(const MachineFunction &MF) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
-                           RegScavenger *Rs = nullptr) const;
+                           RegScavenger *Rs = nullptr) const override;
 
   /// getCrossCopyRegClass - Returns a legal register class to copy a register
   /// in the specified class to or from. Returns original class if it is
   /// possible to copy between a two registers of the specified class.
   const TargetRegisterClass *
-  getCrossCopyRegClass(const TargetRegisterClass *RC) const;
+  getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   /// getLargestLegalSuperClass - Returns the largest super class of RC that is
   /// legal to use in the current sub-target and has the same spill size.
   const TargetRegisterClass*
-  getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
+  getLargestLegalSuperClass(const TargetRegisterClass *RC) const override {
     if (RC == &AArch64::tcGPR64RegClass)
       return &AArch64::GPR64RegClass;
 
     return RC;
   }
 
-  bool requiresRegisterScavenging(const MachineFunction &MF) const {
+  bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool requiresFrameIndexScavenging(const MachineFunction &MF) const {
+  bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
-  bool useFPForScavengingIndex(const MachineFunction &MF) const;
+  bool useFPForScavengingIndex(const MachineFunction &MF) const override;
 };
 
 } // end namespace llvm

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -61,7 +61,7 @@ public:
   AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS,
                    bool LittleEndian);
 
-  virtual bool enableMachineScheduler() const {
+  bool enableMachineScheduler() const override {
     return true;
   }
 

llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

@@ -88,8 +88,8 @@ public:
   }
 
   bool addPreISel() override;
-  virtual bool addInstSelector();
+  bool addInstSelector() override;
-  virtual bool addPreEmitPass();
+  bool addPreEmitPass() override;
 };
 } // namespace
 

llvm/lib/Target/AArch64/AArch64TargetMachine.h

@@ -39,32 +39,32 @@ public:
                        CodeGenOpt::Level OL,
                        bool LittleEndian);
 
-  const AArch64InstrInfo *getInstrInfo() const {
+  const AArch64InstrInfo *getInstrInfo() const override {
     return &InstrInfo;
   }
 
-  const AArch64FrameLowering *getFrameLowering() const {
+  const AArch64FrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
 
-  const AArch64TargetLowering *getTargetLowering() const {
+  const AArch64TargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
 
-  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const {
+  const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
 
-  const AArch64Subtarget *getSubtargetImpl() const { return &Subtarget; }
+  const AArch64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
 
-  const DataLayout *getDataLayout() const { return &DL; }
+  const DataLayout *getDataLayout() const override { return &DL; }
 
-  const TargetRegisterInfo *getRegisterInfo() const {
+  const TargetRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  TargetPassConfig *createPassConfig(PassManagerBase &PM);
+  TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
-  virtual void addAnalysisPasses(PassManagerBase &PM);
+  void addAnalysisPasses(PassManagerBase &PM) override;
 };
 
 // AArch64leTargetMachine - AArch64 little endian target machine.

llvm/lib/Target/AArch64/AArch64TargetObjectFile.h

@@ -23,7 +23,7 @@ namespace llvm {
   /// AArch64ElfTargetObjectFile - This implementation is used for ELF
   /// AArch64 targets.
   class AArch64ElfTargetObjectFile : public TargetLoweringObjectFileELF {
-    virtual void Initialize(MCContext &Ctx, const TargetMachine &TM);
+    void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
   };
 
 } // end namespace llvm

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

@@ -75,7 +75,7 @@ public:
   /// \name Vector TTI Implementations
   /// @{
 
-  unsigned getNumberOfRegisters(bool Vector) const {
+  unsigned getNumberOfRegisters(bool Vector) const override {
     if (Vector) {
       if (ST->hasNEON())
         return 32;
@@ -84,7 +84,7 @@ public:
     return 32;
   }
 
-  unsigned getRegisterBitWidth(bool Vector) const {
+  unsigned getRegisterBitWidth(bool Vector) const override {
     if (Vector) {
       if (ST->hasNEON())
         return 128;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

@@ -65,19 +65,19 @@ public:
   }
 
   // These are the public interface of the MCTargetAsmParser
-  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
+  bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
-                        SMLoc NameLoc,
+                       SMLoc NameLoc,
-                        SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+                       SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
 
-  bool ParseDirective(AsmToken DirectiveID);
+  bool ParseDirective(AsmToken DirectiveID) override;
   bool ParseDirectiveTLSDescCall(SMLoc L);
   bool ParseDirectiveWord(unsigned Size, SMLoc L);
 
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
                                MCStreamer&Out, unsigned &ErrorInfo,
-                               bool MatchingInlineAsm);
+                               bool MatchingInlineAsm) override;
 
   // The rest of the sub-parsers have more freedom over interface: they return
   // an OperandMatchResultTy because it's less ambiguous than true/false or
@@ -235,17 +235,17 @@ public:
   AArch64Operand(const AArch64Operand &o) : MCParsedAsmOperand() {
   }
 
-  SMLoc getStartLoc() const { return StartLoc; }
+  SMLoc getStartLoc() const override { return StartLoc; }
-  SMLoc getEndLoc() const { return EndLoc; }
+  SMLoc getEndLoc() const override { return EndLoc; }
-  void print(raw_ostream&) const;
+  void print(raw_ostream&) const override;
-  void dump() const;
+  void dump() const override;
 
   StringRef getToken() const {
     assert(Kind == k_Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
 
-  unsigned getReg() const {
+  unsigned getReg() const override {
     assert((Kind == k_Register || Kind == k_WrappedRegister)
            && "Invalid access!");
     return Reg.RegNum;
@@ -275,10 +275,10 @@ public:
   }
 
   bool isCondCode() const { return Kind == k_CondCode; }
-  bool isToken() const { return Kind == k_Token; }
+  bool isToken() const override { return Kind == k_Token; }
-  bool isReg() const { return Kind == k_Register; }
+  bool isReg() const override { return Kind == k_Register; }
-  bool isImm() const { return Kind == k_Immediate; }
+  bool isImm() const override { return Kind == k_Immediate; }
-  bool isMem() const { return false; }
+  bool isMem() const override { return false; }
   bool isFPImm() const { return Kind == k_FPImmediate; }
   bool isShiftOrExtend() const { return Kind == k_ShiftExtend; }
   bool isSysReg() const { return Kind == k_SysReg; }

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

@@ -53,7 +53,7 @@ public:
                               const MemoryObject &region,
                               uint64_t address,
                               raw_ostream &vStream,
-                              raw_ostream &cStream) const;
+                              raw_ostream &cStream) const override;
 };
 
 }

llvm/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

@@ -34,7 +34,7 @@ public:
   static const char *getRegisterName(unsigned RegNo);
   static const char *getInstructionName(unsigned Opcode);
 
-  void printRegName(raw_ostream &O, unsigned RegNum) const;
+  void printRegName(raw_ostream &O, unsigned RegNum) const override;
 
   template<unsigned MemSize, unsigned RmSize>
   void printAddrRegExtendOperand(const MCInst *MI, unsigned OpNum,
@@ -159,7 +159,7 @@ public:
 
   void printVPRRegister(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
-  virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
+  void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
 
   bool isStackReg(unsigned RegNo) {
     return RegNo == AArch64::XSP || RegNo == AArch64::WSP;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp

@@ -38,13 +38,13 @@ public:
     delete STI;
   }
 
-  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
+  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override;
 
   virtual void processFixupValue(const MCAssembler &Asm,
                                  const MCAsmLayout &Layout,
                                  const MCFixup &Fixup, const MCFragment *DF,
                                  const MCValue &Target, uint64_t &Value,
-                                 bool &IsResolved);
+                                 bool &IsResolved) override;
 };
 } // end anonymous namespace
 
@@ -89,13 +89,13 @@ public:
   bool fixupNeedsRelaxation(const MCFixup &Fixup,
                             uint64_t Value,
                             const MCRelaxableFragment *DF,
-                            const MCAsmLayout &Layout) const;
+                            const MCAsmLayout &Layout) const override;
 
-  unsigned int getNumFixupKinds() const {
+  unsigned int getNumFixupKinds() const override {
     return AArch64::NumTargetFixupKinds;
   }
 
-  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
+  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
     const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
 // This table *must* be in the order that the fixup_* kinds are defined in
 // AArch64FixupKinds.h.
@@ -177,7 +177,7 @@ public:
   }
 
   void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                  uint64_t Value, bool IsPCRel) const {
+                  uint64_t Value, bool IsPCRel) const override {
     unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8;
     Value = adjustFixupValue(Fixup.getKind(), Value);
     if (!Value) return;           // Doesn't change encoding.
@@ -192,15 +192,15 @@ public:
     }
   }
 
-  bool mayNeedRelaxation(const MCInst&) const {
+  bool mayNeedRelaxation(const MCInst&) const override {
     return false;
   }
 
-  void relaxInstruction(const MCInst&, llvm::MCInst&) const {
+  void relaxInstruction(const MCInst&, llvm::MCInst&) const override {
     llvm_unreachable("Cannot relax instructions");
   }
 
-  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+  MCObjectWriter *createObjectWriter(raw_ostream &OS) const override {
     return createAArch64ELFObjectWriter(OS, OSABI, IsLittle);
   }
 };

llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFStreamer.cpp

@@ -62,8 +62,8 @@ public:
 
   ~AArch64ELFStreamer() {}
 
-  virtual void ChangeSection(const MCSection *Section,
+  void ChangeSection(const MCSection *Section,
-                             const MCExpr *Subsection) {
+                     const MCExpr *Subsection) override {
     // We have to keep track of the mapping symbol state of any sections we
     // use. Each one should start off as EMS_None, which is provided as the
     // default constructor by DenseMap::lookup.
@@ -76,7 +76,8 @@ public:
   /// This function is the one used to emit instruction data into the ELF
   /// streamer. We override it to add the appropriate mapping symbol if
   /// necessary.
-  virtual void EmitInstruction(const MCInst& Inst, const MCSubtargetInfo &STI) {
+  void EmitInstruction(const MCInst& Inst,
+                       const MCSubtargetInfo &STI) override {
     EmitA64MappingSymbol();
     MCELFStreamer::EmitInstruction(Inst, STI);
   }
@@ -84,7 +85,7 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitBytes(StringRef Data) {
+  void EmitBytes(StringRef Data) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitBytes(Data);
   }
@@ -92,8 +93,8 @@ public:
   /// This is one of the functions used to emit data into an ELF section, so the
   /// AArch64 streamer overrides it to add the appropriate mapping symbol ($d)
   /// if necessary.
-  virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
+  void EmitValueImpl(const MCExpr *Value, unsigned Size,
-                             const SMLoc &Loc) {
+                     const SMLoc &Loc) override {
     EmitDataMappingSymbol();
     MCELFStreamer::EmitValueImpl(Value, Size, Loc);
   }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h

@@ -21,7 +21,7 @@ namespace llvm {
 struct AArch64ELFMCAsmInfo : public MCAsmInfoELF {
   explicit AArch64ELFMCAsmInfo(StringRef TT);
 private:
-  virtual void anchor();
+  void anchor() override;
 };
 
 } // namespace llvm

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

@@ -143,7 +143,7 @@ public:
 
   void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
                          SmallVectorImpl<MCFixup> &Fixups,
-                         const MCSubtargetInfo &STI) const;
+                         const MCSubtargetInfo &STI) const override;
 
   template<int hasRs, int hasRt2> unsigned
   fixLoadStoreExclusive(const MCInst &MI, unsigned EncodedValue,

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h

@@ -165,15 +165,15 @@ public:
 
   /// @}
 
-  void PrintImpl(raw_ostream &OS) const;
+  void PrintImpl(raw_ostream &OS) const override;
   bool EvaluateAsRelocatableImpl(MCValue &Res,
-                                 const MCAsmLayout *Layout) const;
+                                 const MCAsmLayout *Layout) const override;
-  void AddValueSymbols(MCAssembler *) const;
+  void AddValueSymbols(MCAssembler *) const override;
-  const MCSection *FindAssociatedSection() const {
+  const MCSection *FindAssociatedSection() const override {
     return getSubExpr()->FindAssociatedSection();
   }
 
-  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const;
+  void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override;
 
   static bool classof(const MCExpr *E) {
     return E->getKind() == MCExpr::Target;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp

@@ -123,14 +123,14 @@ class AArch64MCInstrAnalysis : public MCInstrAnalysis {
 public:
   AArch64MCInstrAnalysis(const MCInstrInfo *Info) : MCInstrAnalysis(Info) {}
 
-  virtual bool isUnconditionalBranch(const MCInst &Inst) const {
+  bool isUnconditionalBranch(const MCInst &Inst) const override {
     if (Inst.getOpcode() == AArch64::Bcc
         && Inst.getOperand(0).getImm() == A64CC::AL)
       return true;
     return MCInstrAnalysis::isUnconditionalBranch(Inst);
   }
 
-  virtual bool isConditionalBranch(const MCInst &Inst) const {
+  bool isConditionalBranch(const MCInst &Inst) const override {
     if (Inst.getOpcode() == AArch64::Bcc
         && Inst.getOperand(0).getImm() == A64CC::AL)
       return false;
@@ -138,7 +138,7 @@ public:
   }
 
   bool evaluateBranch(const MCInst &Inst, uint64_t Addr,
-                      uint64_t Size, uint64_t &Target) const {
+                      uint64_t Size, uint64_t &Target) const override {
     unsigned LblOperand = Inst.getOpcode() == AArch64::Bcc ? 1 : 0;
     // FIXME: We only handle PCRel branches for now.
     if (Info->get(Inst.getOpcode()).OpInfo[LblOperand].OperandType