forked from OSchip/llvm-project
[OpenMP] Support for the num_threads-clause on 'target parallel' on the NVPTX device.
This patch adds support for the Spmd construct 'target parallel' on the NVPTX device. This involves ignoring the num_threads clause on the device since the number of threads in this combined construct is already set on the host through the call to __tgt_target_teams(). Reviewers: ABataev Differential Revision: https://reviews.llvm.org/D29083 llvm-svn: 292999
This commit is contained in:
Arpith Chacko Jacob
parent
99259ee40c
commit
e04da5dee2
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@ -642,6 +642,17 @@ CGOpenMPRuntimeNVPTX::CGOpenMPRuntimeNVPTX(CodeGenModule &CGM)
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llvm_unreachable("OpenMP NVPTX can only handle device code.");
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}
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void CGOpenMPRuntimeNVPTX::emitNumThreadsClause(CodeGenFunction &CGF,
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llvm::Value *NumThreads,
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SourceLocation Loc) {
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// Do nothing in case of Spmd mode and L0 parallel.
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// TODO: If in Spmd mode and L1 parallel emit the clause.
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if (isInSpmdExecutionMode())
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return;
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CGOpenMPRuntime::emitNumThreadsClause(CGF, NumThreads, Loc);
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}
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void CGOpenMPRuntimeNVPTX::emitNumTeamsClause(CodeGenFunction &CGF,
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const Expr *NumTeams,
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const Expr *ThreadLimit,
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@ -170,6 +170,14 @@ protected:
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public:
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explicit CGOpenMPRuntimeNVPTX(CodeGenModule &CGM);
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/// \brief Emits call to void __kmpc_push_num_threads(ident_t *loc, kmp_int32
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/// global_tid, kmp_int32 num_threads) to generate code for 'num_threads'
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/// clause.
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/// \param NumThreads An integer value of threads.
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virtual void emitNumThreadsClause(CodeGenFunction &CGF,
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llvm::Value *NumThreads,
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SourceLocation Loc) override;
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/// \brief This function ought to emit, in the general case, a call to
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// the openmp runtime kmpc_push_num_teams. In NVPTX backend it is not needed
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// as these numbers are obtained through the PTX grid and block configuration.
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@ -0,0 +1,126 @@
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// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// Check that the execution mode of all 2 target regions on the gpu is set to SPMD Mode.
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// CHECK-DAG: {{@__omp_offloading_.+l21}}_exec_mode = weak constant i8 0
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// CHECK-DAG: {{@__omp_offloading_.+l26}}_exec_mode = weak constant i8 0
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target parallel map(tofrom: aa) num_threads(1024)
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{
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aa += 1;
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}
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#pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
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{
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a += 1;
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aa += 1;
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b[2] += 1;
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}
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return a;
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}
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int bar(int n){
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int a = 0;
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a += ftemplate<int>(n);
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return a;
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}
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l21}}(
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]],
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// CHECK: br label {{%?}}[[EXEC:.+]]
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//
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// CHECK: [[EXEC]]
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// CHECK-NOT: call void @__kmpc_push_num_threads
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// CHECK: {{call|invoke}} void [[OP1:@.+]](i32* null, i32* null, i16* [[AA]])
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// CHECK: br label {{%?}}[[DONE:.+]]
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//
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// CHECK: [[DONE]]
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// CHECK: call void @__kmpc_spmd_kernel_deinit()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: }
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// CHECK: define internal void [[OP1]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i16* {{[^%]*}}[[ARG:%.+]])
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// CHECK: = alloca i32*, align
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// CHECK: = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align
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// CHECK: store i16 {{%.+}}, i16* [[AA]], align
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// CHECK: ret void
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// CHECK: }
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l26}}(
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// CHECK: [[A_ADDR:%.+]] = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
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// CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align
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// CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
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// CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align
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// CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
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// CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]],
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// CHECK: br label {{%?}}[[EXEC:.+]]
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//
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// CHECK: [[EXEC]]
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// CHECK-NOT: call void @__kmpc_push_num_threads
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// CHECK: {{call|invoke}} void [[OP2:@.+]](i32* null, i32* null, i32* [[A]], i16* [[AA]], [10 x i32]* [[B]])
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// CHECK: br label {{%?}}[[DONE:.+]]
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//
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// CHECK: [[DONE]]
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// CHECK: call void @__kmpc_spmd_kernel_deinit()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: }
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// CHECK: define internal void [[OP2]](i32* noalias %.global_tid., i32* noalias %.bound_tid., i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]])
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// CHECK: = alloca i32*, align
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// CHECK: = alloca i32*, align
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// CHECK: [[A_ADDR:%.+]] = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
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// CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align
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// CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align
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// CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align
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// CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
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// CHECK: store i32 {{%.+}}, i32* [[A]], align
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// CHECK: store i16 {{%.+}}, i16* [[AA]], align
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// CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]],
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// CHECK: store i32 {{%.+}}, i32* [[ELT]], align
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// CHECK: ret void
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// CHECK: }
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#endif
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