forked from OSchip/llvm-project
[AMDGPU] Move register related queries to subtarget class
Differential Revision: https://reviews.llvm.org/D29318 llvm-svn: 294440
This commit is contained in:
Konstantin Zhuravlyov
parent
fd0dda765e
commit
e03b1d7b6a
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@ -473,26 +473,12 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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ExtraSGPRs = 6;
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}
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// Record first reserved register and reserved register count fields, and
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// update max register counts if "amdgpu-debugger-reserve-regs" attribute was
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// requested.
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ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
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ProgInfo.ReservedVGPRCount = RI->getNumDebuggerReservedVGPRs(STM);
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// Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
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// DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
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// attribute was requested.
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if (STM.debuggerEmitPrologue()) {
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ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
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RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
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ProgInfo.DebuggerPrivateSegmentBufferSGPR =
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RI->getHWRegIndex(MFI->getScratchRSrcReg());
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}
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unsigned ExtraVGPRs = STM.getReservedNumVGPRs(MF);
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// Check the addressable register limit before we add ExtraSGPRs.
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if (STM.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS &&
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!STM.hasSGPRInitBug()) {
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unsigned MaxAddressableNumSGPRs = STM.getMaxNumSGPRs();
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unsigned MaxAddressableNumSGPRs = STM.getAddressableNumSGPRs();
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if (MaxSGPR + 1 > MaxAddressableNumSGPRs) {
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// This can happen due to a compiler bug or when using inline asm.
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LLVMContext &Ctx = MF.getFunction()->getContext();
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@ -507,23 +493,23 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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// Account for extra SGPRs and VGPRs reserved for debugger use.
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MaxSGPR += ExtraSGPRs;
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MaxVGPR += RI->getNumDebuggerReservedVGPRs(STM);
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MaxVGPR += ExtraVGPRs;
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// We found the maximum register index. They start at 0, so add one to get the
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// number of registers.
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ProgInfo.NumVGPR = MaxVGPR + 1;
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ProgInfo.NumSGPR = MaxSGPR + 1;
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ProgInfo.NumVGPR = MaxVGPR + 1;
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// Adjust number of registers used to meet default/requested minimum/maximum
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// number of waves per execution unit request.
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ProgInfo.NumSGPRsForWavesPerEU = std::max(
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ProgInfo.NumSGPR, RI->getMinNumSGPRs(STM, MFI->getMaxWavesPerEU()));
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ProgInfo.NumSGPR, STM.getMinNumSGPRs(MFI->getMaxWavesPerEU()));
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ProgInfo.NumVGPRsForWavesPerEU = std::max(
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ProgInfo.NumVGPR, RI->getMinNumVGPRs(MFI->getMaxWavesPerEU()));
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ProgInfo.NumVGPR, STM.getMinNumVGPRs(MFI->getMaxWavesPerEU()));
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if (STM.getGeneration() <= AMDGPUSubtarget::SEA_ISLANDS ||
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STM.hasSGPRInitBug()) {
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unsigned MaxNumSGPRs = STM.getMaxNumSGPRs();
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unsigned MaxNumSGPRs = STM.getAddressableNumSGPRs();
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if (ProgInfo.NumSGPR > MaxNumSGPRs) {
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// This can happen due to a compiler bug or when using inline asm to use the
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// registers which are usually reserved for vcc etc.
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@ -560,13 +546,29 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
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// SGPRBlocks is actual number of SGPR blocks minus 1.
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ProgInfo.SGPRBlocks = alignTo(ProgInfo.NumSGPRsForWavesPerEU,
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RI->getSGPRAllocGranule());
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ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / RI->getSGPRAllocGranule() - 1;
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STM.getSGPRAllocGranule());
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ProgInfo.SGPRBlocks = ProgInfo.SGPRBlocks / STM.getSGPRAllocGranule() - 1;
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// VGPRBlocks is actual number of VGPR blocks minus 1.
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ProgInfo.VGPRBlocks = alignTo(ProgInfo.NumVGPRsForWavesPerEU,
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RI->getVGPRAllocGranule());
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ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / RI->getVGPRAllocGranule() - 1;
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STM.getVGPRAllocGranule());
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ProgInfo.VGPRBlocks = ProgInfo.VGPRBlocks / STM.getVGPRAllocGranule() - 1;
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// Record first reserved register and reserved register count fields, and
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// update max register counts if "amdgpu-debugger-reserve-regs" attribute was
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// requested.
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ProgInfo.ReservedVGPRFirst = STM.debuggerReserveRegs() ? MaxVGPR + 1 : 0;
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ProgInfo.ReservedVGPRCount = STM.getReservedNumVGPRs(MF);
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// Update DebuggerWavefrontPrivateSegmentOffsetSGPR and
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// DebuggerPrivateSegmentBufferSGPR fields if "amdgpu-debugger-emit-prologue"
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// attribute was requested.
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if (STM.debuggerEmitPrologue()) {
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ProgInfo.DebuggerWavefrontPrivateSegmentOffsetSGPR =
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RI->getHWRegIndex(MFI->getScratchWaveOffsetReg());
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ProgInfo.DebuggerPrivateSegmentBufferSGPR =
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RI->getHWRegIndex(MFI->getScratchRSrcReg());
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}
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// Set the value to initialize FP_ROUND and FP_DENORM parts of the mode
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// register.
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@ -13,6 +13,7 @@
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//===----------------------------------------------------------------------===//
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#include "AMDGPUSubtarget.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/Target/TargetFrameLowering.h"
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@ -322,12 +323,179 @@ unsigned SISubtarget::getOccupancyWithNumVGPRs(unsigned VGPRs) const {
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return 1;
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}
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unsigned SISubtarget::getMaxNumSGPRs() const {
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if (hasSGPRInitBug())
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return SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
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if (getGeneration() >= VOLCANIC_ISLANDS)
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return 102;
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return 104;
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unsigned SISubtarget::getMinNumSGPRs(unsigned WavesPerEU) const {
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if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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switch (WavesPerEU) {
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case 0: return 0;
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case 10: return 0;
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case 9: return 0;
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case 8: return 81;
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default: return 97;
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}
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} else {
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switch (WavesPerEU) {
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case 0: return 0;
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case 10: return 0;
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case 9: return 49;
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case 8: return 57;
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case 7: return 65;
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case 6: return 73;
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case 5: return 81;
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default: return 97;
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}
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}
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}
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unsigned SISubtarget::getMaxNumSGPRs(unsigned WavesPerEU,
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bool Addressable) const {
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if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
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switch (WavesPerEU) {
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case 0: return 80;
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case 10: return 80;
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case 9: return 80;
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case 8: return 96;
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default: return Addressable ? getAddressableNumSGPRs() : 112;
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}
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} else {
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switch (WavesPerEU) {
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case 0: return 48;
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case 10: return 48;
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case 9: return 56;
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case 8: return 64;
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case 7: return 72;
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case 6: return 80;
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case 5: return 96;
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default: return getAddressableNumSGPRs();
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}
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}
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}
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unsigned SISubtarget::getReservedNumSGPRs(const MachineFunction &MF) const {
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const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
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if (MFI.hasFlatScratchInit()) {
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if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
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return 6; // FLAT_SCRATCH, XNACK, VCC (in that order).
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if (getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
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return 4; // FLAT_SCRATCH, VCC (in that order).
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}
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if (isXNACKEnabled())
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return 4; // XNACK, VCC (in that order).
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return 2; // VCC.
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}
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unsigned SISubtarget::getMaxNumSGPRs(const MachineFunction &MF) const {
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const Function &F = *MF.getFunction();
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const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
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// Compute maximum number of SGPRs function can use using default/requested
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// minimum number of waves per execution unit.
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std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU();
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unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false);
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unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true);
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// Check if maximum number of SGPRs was explicitly requested using
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// "amdgpu-num-sgpr" attribute.
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if (F.hasFnAttribute("amdgpu-num-sgpr")) {
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unsigned Requested = AMDGPU::getIntegerAttribute(
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F, "amdgpu-num-sgpr", MaxNumSGPRs);
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// Make sure requested value does not violate subtarget's specifications.
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if (Requested && (Requested <= getReservedNumSGPRs(MF)))
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Requested = 0;
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// If more SGPRs are required to support the input user/system SGPRs,
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// increase to accommodate them.
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//
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// FIXME: This really ends up using the requested number of SGPRs + number
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// of reserved special registers in total. Theoretically you could re-use
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// the last input registers for these special registers, but this would
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// require a lot of complexity to deal with the weird aliasing.
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unsigned InputNumSGPRs = MFI.getNumPreloadedSGPRs();
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if (Requested && Requested < InputNumSGPRs)
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Requested = InputNumSGPRs;
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// Make sure requested value is compatible with values implied by
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// default/requested minimum/maximum number of waves per execution unit.
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if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false))
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Requested = 0;
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if (WavesPerEU.second &&
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Requested && Requested < getMinNumSGPRs(WavesPerEU.second))
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Requested = 0;
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if (Requested)
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MaxNumSGPRs = Requested;
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}
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if (hasSGPRInitBug())
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MaxNumSGPRs = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
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return std::min(MaxNumSGPRs - getReservedNumSGPRs(MF),
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MaxAddressableNumSGPRs);
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}
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unsigned SISubtarget::getMinNumVGPRs(unsigned WavesPerEU) const {
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switch (WavesPerEU) {
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case 0: return 0;
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case 10: return 0;
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case 9: return 25;
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case 8: return 29;
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case 7: return 33;
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case 6: return 37;
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case 5: return 41;
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case 4: return 49;
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case 3: return 65;
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case 2: return 85;
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default: return 129;
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}
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}
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unsigned SISubtarget::getMaxNumVGPRs(unsigned WavesPerEU) const {
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switch (WavesPerEU) {
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case 0: return 24;
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case 10: return 24;
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case 9: return 28;
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case 8: return 32;
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case 7: return 36;
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case 6: return 40;
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case 5: return 48;
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case 4: return 64;
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case 3: return 84;
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case 2: return 128;
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default: return getTotalNumVGPRs();
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}
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}
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unsigned SISubtarget::getMaxNumVGPRs(const MachineFunction &MF) const {
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const Function &F = *MF.getFunction();
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const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
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// Compute maximum number of VGPRs function can use using default/requested
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// minimum number of waves per execution unit.
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std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU();
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unsigned MaxNumVGPRs = getMaxNumVGPRs(WavesPerEU.first);
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// Check if maximum number of VGPRs was explicitly requested using
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// "amdgpu-num-vgpr" attribute.
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if (F.hasFnAttribute("amdgpu-num-vgpr")) {
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unsigned Requested = AMDGPU::getIntegerAttribute(
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F, "amdgpu-num-vgpr", MaxNumVGPRs);
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// Make sure requested value does not violate subtarget's specifications.
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if (Requested && Requested <= getReservedNumVGPRs(MF))
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Requested = 0;
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// Make sure requested value is compatible with values implied by
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// default/requested minimum/maximum number of waves per execution unit.
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if (Requested && Requested > getMaxNumVGPRs(WavesPerEU.first))
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Requested = 0;
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if (WavesPerEU.second &&
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Requested && Requested < getMinNumVGPRs(WavesPerEU.second))
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Requested = 0;
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if (Requested)
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MaxNumVGPRs = Requested;
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}
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return MaxNumVGPRs - getReservedNumVGPRs(MF);
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}
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@ -642,7 +642,85 @@ public:
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return true;
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}
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unsigned getMaxNumSGPRs() const;
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/// \returns SGPR allocation granularity supported by the subtarget.
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unsigned getSGPRAllocGranule() const {
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return 8;
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}
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/// \returns Total number of SGPRs supported by the subtarget.
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unsigned getTotalNumSGPRs() const {
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if (getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
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return 800;
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return 512;
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}
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/// \returns Addressable number of SGPRs supported by the subtarget.
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unsigned getAddressableNumSGPRs() const {
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if (hasSGPRInitBug())
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return SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
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if (getGeneration() >= VOLCANIC_ISLANDS)
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return 102;
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return 104;
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}
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/// \returns Minimum number of SGPRs that meets the given number of waves per
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/// execution unit requirement supported by the subtarget.
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unsigned getMinNumSGPRs(unsigned WavesPerEU) const;
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/// \returns Maximum number of SGPRs that meets the given number of waves per
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/// execution unit requirement supported by the subtarget.
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unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const;
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/// \returns Reserved number of SGPRs for given function \p MF.
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unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
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/// \returns Maximum number of SGPRs that meets number of waves per execution
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/// unit requirement for function \p MF, or number of SGPRs explicitly
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/// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
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///
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/// \returns Value that meets number of waves per execution unit requirement
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/// if explicitly requested value cannot be converted to integer, violates
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/// subtarget's specifications, or does not meet number of waves per execution
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/// unit requirement.
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unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
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/// \returns VGPR allocation granularity supported by the subtarget.
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unsigned getVGPRAllocGranule() const {
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return 4;
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}
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/// \returns Total number of VGPRs supported by the subtarget.
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unsigned getTotalNumVGPRs() const {
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return 256;
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}
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/// \returns Addressable number of VGPRs supported by the subtarget.
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unsigned getAddressableNumVGPRs() const {
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return getTotalNumVGPRs();
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}
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/// \returns Minimum number of VGPRs that meets given number of waves per
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/// execution unit requirement supported by the subtarget.
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unsigned getMinNumVGPRs(unsigned WavesPerEU) const;
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/// \returns Maximum number of VGPRs that meets given number of waves per
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/// execution unit requirement supported by the subtarget.
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unsigned getMaxNumVGPRs(unsigned WavesPerEU) const;
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/// \returns Reserved number of VGPRs for given function \p MF.
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unsigned getReservedNumVGPRs(const MachineFunction &MF) const {
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return debuggerReserveRegs() ? 4 : 0;
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}
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/// \returns Maximum number of VGPRs that meets number of waves per execution
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/// unit requirement for function \p MF, or number of VGPRs explicitly
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/// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
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///
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/// \returns Value that meets number of waves per execution unit requirement
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/// if explicitly requested value cannot be converted to integer, violates
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/// subtarget's specifications, or does not meet number of waves per execution
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/// unit requirement.
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unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
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};
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} // end namespace llvm
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@ -145,8 +145,8 @@ void GCNMaxOccupancySchedStrategy::pickNodeFromQueue(SchedBoundary &Zone,
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unsigned VGPRExcessLimit =
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Context->RegClassInfo->getNumAllocatableRegs(&AMDGPU::VGPR_32RegClass);
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unsigned MaxWaves = getMaxWaves(SGPRPressure, VGPRPressure, DAG->MF);
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unsigned SGPRCriticalLimit = SRI->getMaxNumSGPRs(ST, MaxWaves, true);
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unsigned VGPRCriticalLimit = SRI->getMaxNumVGPRs(MaxWaves);
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unsigned SGPRCriticalLimit = ST.getMaxNumSGPRs(MaxWaves, true);
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unsigned VGPRCriticalLimit = ST.getMaxNumVGPRs(MaxWaves);
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ReadyQueue &Q = Zone.Available;
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for (SUnit *SU : Q) {
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@ -21,16 +21,16 @@
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using namespace llvm;
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static ArrayRef<MCPhysReg> getAllSGPR128(const MachineFunction &MF,
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const SIRegisterInfo *TRI) {
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static ArrayRef<MCPhysReg> getAllSGPR128(const SISubtarget &ST,
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const MachineFunction &MF) {
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return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
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TRI->getMaxNumSGPRs(MF) / 4);
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ST.getMaxNumSGPRs(MF) / 4);
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}
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static ArrayRef<MCPhysReg> getAllSGPRs(const MachineFunction &MF,
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const SIRegisterInfo *TRI) {
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static ArrayRef<MCPhysReg> getAllSGPRs(const SISubtarget &ST,
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const MachineFunction &MF) {
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return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
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TRI->getMaxNumSGPRs(MF));
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ST.getMaxNumSGPRs(MF));
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}
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void SIFrameLowering::emitFlatScratchInit(const SIInstrInfo *TII,
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@ -111,7 +111,7 @@ unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
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MachineRegisterInfo &MRI = MF.getRegInfo();
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|
||||
unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 3) / 4;
|
||||
ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(MF, TRI);
|
||||
ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
|
||||
AllSGPR128s = AllSGPR128s.slice(std::min(static_cast<unsigned>(AllSGPR128s.size()), NumPreloaded));
|
||||
|
||||
// Skip the last 2 elements because the last one is reserved for VCC, and
|
||||
|
|
@ -146,7 +146,7 @@ unsigned SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
|
|||
|
||||
unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
|
||||
|
||||
ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(MF, TRI);
|
||||
ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
|
||||
if (NumPreloaded > AllSGPRs.size())
|
||||
return ScratchWaveOffsetReg;
|
||||
|
||||
|
|
|
|||
|
|
@ -97,14 +97,18 @@ void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) co
|
|||
|
||||
unsigned SIRegisterInfo::reservedPrivateSegmentBufferReg(
|
||||
const MachineFunction &MF) const {
|
||||
unsigned BaseIdx = alignDown(getMaxNumSGPRs(MF), 4) - 4;
|
||||
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4;
|
||||
unsigned BaseReg(AMDGPU::SGPR_32RegClass.getRegister(BaseIdx));
|
||||
return getMatchingSuperReg(BaseReg, AMDGPU::sub0, &AMDGPU::SReg_128RegClass);
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::reservedPrivateSegmentWaveByteOffsetReg(
|
||||
const MachineFunction &MF) const {
|
||||
unsigned RegCount = getMaxNumSGPRs(MF);
|
||||
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
unsigned RegCount = ST.getMaxNumSGPRs(MF);
|
||||
unsigned Reg;
|
||||
|
||||
// Try to place it in a hole after PrivateSegmentbufferReg.
|
||||
|
|
@ -139,14 +143,16 @@ BitVector SIRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
|
|||
reserveRegisterTuples(Reserved, AMDGPU::TTMP8_TTMP9);
|
||||
reserveRegisterTuples(Reserved, AMDGPU::TTMP10_TTMP11);
|
||||
|
||||
unsigned MaxNumSGPRs = getMaxNumSGPRs(MF);
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
|
||||
unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF);
|
||||
unsigned TotalNumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
|
||||
for (unsigned i = MaxNumSGPRs; i < TotalNumSGPRs; ++i) {
|
||||
unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
|
||||
reserveRegisterTuples(Reserved, Reg);
|
||||
}
|
||||
|
||||
unsigned MaxNumVGPRs = getMaxNumVGPRs(MF);
|
||||
unsigned MaxNumVGPRs = ST.getMaxNumVGPRs(MF);
|
||||
unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
|
||||
for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i) {
|
||||
unsigned Reg = AMDGPU::VGPR_32RegClass.getRegister(i);
|
||||
|
|
@ -1156,210 +1162,6 @@ SIRegisterInfo::findUnusedRegister(const MachineRegisterInfo &MRI,
|
|||
return AMDGPU::NoRegister;
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getTotalNumSGPRs(const SISubtarget &ST) const {
|
||||
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
|
||||
return 800;
|
||||
return 512;
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getNumAddressableSGPRs(const SISubtarget &ST) const {
|
||||
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
|
||||
return 102;
|
||||
return 104;
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getNumReservedSGPRs(const SISubtarget &ST,
|
||||
const SIMachineFunctionInfo &MFI) const {
|
||||
if (MFI.hasFlatScratchInit()) {
|
||||
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS)
|
||||
return 6; // FLAT_SCRATCH, XNACK, VCC (in that order)
|
||||
|
||||
if (ST.getGeneration() == AMDGPUSubtarget::SEA_ISLANDS)
|
||||
return 4; // FLAT_SCRATCH, VCC (in that order)
|
||||
}
|
||||
|
||||
if (ST.isXNACKEnabled())
|
||||
return 4; // XNACK, VCC (in that order)
|
||||
|
||||
return 2; // VCC.
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMinNumSGPRs(const SISubtarget &ST,
|
||||
unsigned WavesPerEU) const {
|
||||
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 0;
|
||||
case 10: return 0;
|
||||
case 9: return 0;
|
||||
case 8: return 81;
|
||||
default: return 97;
|
||||
}
|
||||
} else {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 0;
|
||||
case 10: return 0;
|
||||
case 9: return 49;
|
||||
case 8: return 57;
|
||||
case 7: return 65;
|
||||
case 6: return 73;
|
||||
case 5: return 81;
|
||||
default: return 97;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMaxNumSGPRs(const SISubtarget &ST,
|
||||
unsigned WavesPerEU,
|
||||
bool Addressable) const {
|
||||
if (ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 80;
|
||||
case 10: return 80;
|
||||
case 9: return 80;
|
||||
case 8: return 96;
|
||||
default: return Addressable ? getNumAddressableSGPRs(ST) : 112;
|
||||
}
|
||||
} else {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 48;
|
||||
case 10: return 48;
|
||||
case 9: return 56;
|
||||
case 8: return 64;
|
||||
case 7: return 72;
|
||||
case 6: return 80;
|
||||
case 5: return 96;
|
||||
default: return getNumAddressableSGPRs(ST);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMaxNumSGPRs(const MachineFunction &MF) const {
|
||||
const Function &F = *MF.getFunction();
|
||||
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
|
||||
|
||||
// Compute maximum number of SGPRs function can use using default/requested
|
||||
// minimum number of waves per execution unit.
|
||||
std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU();
|
||||
unsigned MaxNumSGPRs = getMaxNumSGPRs(ST, WavesPerEU.first, false);
|
||||
unsigned MaxNumAddressableSGPRs = getMaxNumSGPRs(ST, WavesPerEU.first, true);
|
||||
|
||||
// Check if maximum number of SGPRs was explicitly requested using
|
||||
// "amdgpu-num-sgpr" attribute.
|
||||
if (F.hasFnAttribute("amdgpu-num-sgpr")) {
|
||||
unsigned Requested = AMDGPU::getIntegerAttribute(
|
||||
F, "amdgpu-num-sgpr", MaxNumSGPRs);
|
||||
|
||||
// Make sure requested value does not violate subtarget's specifications.
|
||||
if (Requested && (Requested <= getNumReservedSGPRs(ST, MFI)))
|
||||
Requested = 0;
|
||||
|
||||
// If more SGPRs are required to support the input user/system SGPRs,
|
||||
// increase to accommodate them.
|
||||
//
|
||||
// FIXME: This really ends up using the requested number of SGPRs + number
|
||||
// of reserved special registers in total. Theoretically you could re-use
|
||||
// the last input registers for these special registers, but this would
|
||||
// require a lot of complexity to deal with the weird aliasing.
|
||||
unsigned NumInputSGPRs = MFI.getNumPreloadedSGPRs();
|
||||
if (Requested && Requested < NumInputSGPRs)
|
||||
Requested = NumInputSGPRs;
|
||||
|
||||
// Make sure requested value is compatible with values implied by
|
||||
// default/requested minimum/maximum number of waves per execution unit.
|
||||
if (Requested && Requested > getMaxNumSGPRs(ST, WavesPerEU.first, false))
|
||||
Requested = 0;
|
||||
if (WavesPerEU.second &&
|
||||
Requested && Requested < getMinNumSGPRs(ST, WavesPerEU.second))
|
||||
Requested = 0;
|
||||
|
||||
if (Requested)
|
||||
MaxNumSGPRs = Requested;
|
||||
}
|
||||
|
||||
if (ST.hasSGPRInitBug())
|
||||
MaxNumSGPRs = SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
|
||||
|
||||
return std::min(MaxNumSGPRs - getNumReservedSGPRs(ST, MFI),
|
||||
MaxNumAddressableSGPRs);
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getNumDebuggerReservedVGPRs(
|
||||
const SISubtarget &ST) const {
|
||||
if (ST.debuggerReserveRegs())
|
||||
return 4;
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMinNumVGPRs(unsigned WavesPerEU) const {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 0;
|
||||
case 10: return 0;
|
||||
case 9: return 25;
|
||||
case 8: return 29;
|
||||
case 7: return 33;
|
||||
case 6: return 37;
|
||||
case 5: return 41;
|
||||
case 4: return 49;
|
||||
case 3: return 65;
|
||||
case 2: return 85;
|
||||
default: return 129;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMaxNumVGPRs(unsigned WavesPerEU) const {
|
||||
switch (WavesPerEU) {
|
||||
case 0: return 24;
|
||||
case 10: return 24;
|
||||
case 9: return 28;
|
||||
case 8: return 32;
|
||||
case 7: return 36;
|
||||
case 6: return 40;
|
||||
case 5: return 48;
|
||||
case 4: return 64;
|
||||
case 3: return 84;
|
||||
case 2: return 128;
|
||||
default: return getTotalNumVGPRs();
|
||||
}
|
||||
}
|
||||
|
||||
unsigned SIRegisterInfo::getMaxNumVGPRs(const MachineFunction &MF) const {
|
||||
const Function &F = *MF.getFunction();
|
||||
|
||||
const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
|
||||
const SIMachineFunctionInfo &MFI = *MF.getInfo<SIMachineFunctionInfo>();
|
||||
|
||||
// Compute maximum number of VGPRs function can use using default/requested
|
||||
// minimum number of waves per execution unit.
|
||||
std::pair<unsigned, unsigned> WavesPerEU = MFI.getWavesPerEU();
|
||||
unsigned MaxNumVGPRs = getMaxNumVGPRs(WavesPerEU.first);
|
||||
|
||||
// Check if maximum number of VGPRs was explicitly requested using
|
||||
// "amdgpu-num-vgpr" attribute.
|
||||
if (F.hasFnAttribute("amdgpu-num-vgpr")) {
|
||||
unsigned Requested = AMDGPU::getIntegerAttribute(
|
||||
F, "amdgpu-num-vgpr", MaxNumVGPRs);
|
||||
|
||||
// Make sure requested value does not violate subtarget's specifications.
|
||||
if (Requested && Requested <= getNumDebuggerReservedVGPRs(ST))
|
||||
Requested = 0;
|
||||
|
||||
// Make sure requested value is compatible with values implied by
|
||||
// default/requested minimum/maximum number of waves per execution unit.
|
||||
if (Requested && Requested > getMaxNumVGPRs(WavesPerEU.first))
|
||||
Requested = 0;
|
||||
if (WavesPerEU.second &&
|
||||
Requested && Requested < getMinNumVGPRs(WavesPerEU.second))
|
||||
Requested = 0;
|
||||
|
||||
if (Requested)
|
||||
MaxNumVGPRs = Requested;
|
||||
}
|
||||
|
||||
return MaxNumVGPRs - getNumDebuggerReservedVGPRs(ST);
|
||||
}
|
||||
|
||||
ArrayRef<int16_t> SIRegisterInfo::getRegSplitParts(const TargetRegisterClass *RC,
|
||||
unsigned EltSize) const {
|
||||
if (EltSize == 4) {
|
||||
|
|
|
|||
|
|
@ -195,72 +195,6 @@ public:
|
|||
return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
|
||||
}
|
||||
|
||||
/// \returns SGPR allocation granularity supported by the subtarget.
|
||||
unsigned getSGPRAllocGranule() const {
|
||||
return 8;
|
||||
}
|
||||
|
||||
/// \returns Total number of SGPRs supported by the subtarget.
|
||||
unsigned getTotalNumSGPRs(const SISubtarget &ST) const;
|
||||
|
||||
/// \returns Number of addressable SGPRs supported by the subtarget.
|
||||
unsigned getNumAddressableSGPRs(const SISubtarget &ST) const;
|
||||
|
||||
/// \returns Number of reserved SGPRs supported by the subtarget.
|
||||
unsigned getNumReservedSGPRs(const SISubtarget &ST,
|
||||
const SIMachineFunctionInfo &MFI) const;
|
||||
|
||||
/// \returns Minimum number of SGPRs that meets given number of waves per
|
||||
/// execution unit requirement for given subtarget.
|
||||
unsigned getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const;
|
||||
|
||||
/// \returns Maximum number of SGPRs that meets given number of waves per
|
||||
/// execution unit requirement for given subtarget.
|
||||
unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU,
|
||||
bool Addressable) const;
|
||||
|
||||
/// \returns Maximum number of SGPRs that meets number of waves per execution
|
||||
/// unit requirement for function \p MF, or number of SGPRs explicitly
|
||||
/// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
|
||||
///
|
||||
/// \returns Value that meets number of waves per execution unit requirement
|
||||
/// if explicitly requested value cannot be converted to integer, violates
|
||||
/// subtarget's specifications, or does not meet number of waves per execution
|
||||
/// unit requirement.
|
||||
unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
|
||||
|
||||
/// \returns VGPR allocation granularity supported by the subtarget.
|
||||
unsigned getVGPRAllocGranule() const {
|
||||
return 4;
|
||||
}
|
||||
|
||||
/// \returns Total number of VGPRs supported by the subtarget.
|
||||
unsigned getTotalNumVGPRs() const {
|
||||
return 256;
|
||||
}
|
||||
|
||||
/// \returns Number of reserved VGPRs for debugger use supported by the
|
||||
/// subtarget.
|
||||
unsigned getNumDebuggerReservedVGPRs(const SISubtarget &ST) const;
|
||||
|
||||
/// \returns Minimum number of SGPRs that meets given number of waves per
|
||||
/// execution unit requirement.
|
||||
unsigned getMinNumVGPRs(unsigned WavesPerEU) const;
|
||||
|
||||
/// \returns Maximum number of VGPRs that meets given number of waves per
|
||||
/// execution unit requirement.
|
||||
unsigned getMaxNumVGPRs(unsigned WavesPerEU) const;
|
||||
|
||||
/// \returns Maximum number of VGPRs that meets number of waves per execution
|
||||
/// unit requirement for function \p MF, or number of VGPRs explicitly
|
||||
/// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
|
||||
///
|
||||
/// \returns Value that meets number of waves per execution unit requirement
|
||||
/// if explicitly requested value cannot be converted to integer, violates
|
||||
/// subtarget's specifications, or does not meet number of waves per execution
|
||||
/// unit requirement.
|
||||
unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
|
||||
|
||||
ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
|
||||
unsigned EltSize) const;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue