rename PPC::COND_BRANCH to PPC::BCC

llvm-svn: 31834

llvm/lib/Target/PowerPC/PPCBranchSelector.cpp

@@ -54,7 +54,7 @@ FunctionPass *llvm::createPPCBranchSelectionPass() {
 ///
 static unsigned getNumBytesForInstruction(MachineInstr *MI) {
   switch (MI->getOpcode()) {
-  case PPC::COND_BRANCH:
+  case PPC::BCC:
     // while this will be 4 most of the time, if we emit 8 it is just a
     // minor pessimization that saves us from having to worry about
     // keeping the offsets up to date later when we emit long branch glue.
@@ -116,7 +116,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
       // We may end up deleting the MachineInstr that MBBI points to, so
       // remember its opcode now so we can refer to it after calling erase()
       unsigned ByteSize = getNumBytesForInstruction(MBBI);
-      if (MBBI->getOpcode() != PPC::COND_BRANCH) {
+      if (MBBI->getOpcode() != PPC::BCC) {
         ByteCount += ByteSize;
         continue;
       }
@@ -159,7 +159,7 @@ bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) {
         MBBJ = BuildMI(*MBB, MBBI, PPC::B, 1).addMBB(DestMBB);
       }
       
-      // Erase the psuedo COND_BRANCH instruction, and then back up the
+      // Erase the psuedo BCC instruction, and then back up the
       // iterator so that when the for loop increments it, we end up in
       // the correct place rather than iterating off the end.
       MBB->erase(MBBI);

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

@@ -1007,7 +1007,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
     SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
     SDOperand Ops[] = { CondCode, getI32Imm(getPredicateForSetCC(CC)), 
                         N->getOperand(4), N->getOperand(0) };
-    return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
+    return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
   }
   case ISD::BRIND: {
     // FIXME: Should custom lower this.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

@@ -2613,7 +2613,7 @@ PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
   MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
   MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
   unsigned SelectPred = MI->getOperand(4).getImm();
-  BuildMI(BB, PPC::COND_BRANCH, 3)
+  BuildMI(BB, PPC::BCC, 3)
     .addReg(MI->getOperand(1).getReg()).addImm(SelectPred).addMBB(sinkMBB);
   MachineFunction *F = BB->getParent();
   F->getBasicBlockList().insert(It, copy0MBB);

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

@@ -192,7 +192,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
     if (LastInst->getOpcode() == PPC::B) {
       TBB = LastInst->getOperand(0).getMachineBasicBlock();
       return false;
-    } else if (LastInst->getOpcode() == PPC::COND_BRANCH) {
+    } else if (LastInst->getOpcode() == PPC::BCC) {
       // Block ends with fall-through condbranch.
       TBB = LastInst->getOperand(2).getMachineBasicBlock();
       Cond.push_back(LastInst->getOperand(0));
@@ -211,8 +211,8 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
       isTerminatorInstr((--I)->getOpcode()))
     return true;
   
-  // If the block ends with PPC::B and PPC:COND_BRANCH, handle it.
+  // If the block ends with PPC::B and PPC:BCC, handle it.
-  if (SecondLastInst->getOpcode() == PPC::COND_BRANCH && 
+  if (SecondLastInst->getOpcode() == PPC::BCC && 
       LastInst->getOpcode() == PPC::B) {
     TBB =  SecondLastInst->getOperand(2).getMachineBasicBlock();
     Cond.push_back(SecondLastInst->getOperand(0));
@@ -229,7 +229,7 @@ void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
   MachineBasicBlock::iterator I = MBB.end();
   if (I == MBB.begin()) return;
   --I;
-  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::COND_BRANCH)
+  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
     return;
   
   // Remove the branch.
@@ -239,7 +239,7 @@ void PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
 
   if (I == MBB.begin()) return;
   --I;
-  if (I->getOpcode() != PPC::COND_BRANCH)
+  if (I->getOpcode() != PPC::BCC)
     return;
   
   // Remove the branch.
@@ -259,13 +259,13 @@ void PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     if (Cond.empty())   // Unconditional branch
       BuildMI(&MBB, PPC::B, 1).addMBB(TBB);
     else                // Conditional branch
-      BuildMI(&MBB, PPC::COND_BRANCH, 3)
+      BuildMI(&MBB, PPC::BCC, 3)
         .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
     return;
   }
   
   // Two-way Conditional Branch.
-  BuildMI(&MBB, PPC::COND_BRANCH, 3)
+  BuildMI(&MBB, PPC::BCC, 3)
     .addReg(Cond[0].getReg()).addImm(Cond[1].getImm()).addMBB(TBB);
   BuildMI(&MBB, PPC::B, 1).addMBB(FBB);
 }

llvm/lib/Target/PowerPC/PPCInstrInfo.td

@@ -352,17 +352,18 @@ let Defs = [LR] in
 
 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, 
     noResults = 1, PPC970_Unit = 7 in {
-  // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
-  // 'opc' is a 'PPC::Predicate' value.
-  def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
-                           "${:comment} COND_BRANCH $crS, $opc, $dst",
-                           [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
   let isBarrier = 1 in {
   def B   : IForm<18, 0, 0, (ops target:$dst),
                   "b $dst", BrB,
                   [(br bb:$dst)]>;
   }
 
+  // BCC is formed before branch selection, it is turned into Bxx below.
+  // 'opc' is a 'PPC::Predicate' value.
+  def BCC : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
+                   "${:comment} BCC $crS, $opc, $dst",
+                   [(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
+
   def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
                   "blt $crS, $block", BrB>;
   def BLE : BForm<16, 0, 0, 4,  1, (ops CRRC:$crS, target:$block),