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AMDGPU/GlobalISel: Legalize/regbankselect fneg/fabs/fsub 

llvm-svn: 349463
This commit is contained in:
Matt Arsenault 2018-12-18 09:19:03 +00:00
parent 8488a44c34
commit e01e7c81f2
7 changed files with 166 additions and 2 deletions
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8
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
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@ -91,9 +91,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
setAction({G_CONSTANT, S1}, Legal);
getActionDefinitionsBuilder(
{ G_FADD, G_FMUL })
{ G_FADD, G_FMUL, G_FNEG, G_FABS})
.legalFor({S32, S64});
// Use actual fsub instruction
setAction({G_FSUB, S32}, Legal);
// Must use fadd + fneg
setAction({G_FSUB, S64}, Lower);
setAction({G_FCMP, S1}, Legal);
setAction({G_FCMP, 1, S32}, Legal);
setAction({G_FCMP, 1, S64}, Legal);

4
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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@ -411,7 +411,9 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_CTTZ:
case AMDGPU::G_CTTZ_ZERO_UNDEF:
case AMDGPU::G_CTPOP:
case AMDGPU::G_BSWAP: {
case AMDGPU::G_BSWAP:
case AMDGPU::G_FABS:
case AMDGPU::G_FNEG: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
OpdsMapping[0] = OpdsMapping[1] = AMDGPU::getValueMapping(BankID, Size);

25
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir Normal file
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@ -0,0 +1,25 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_fabs_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fabs_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FABS %0
...
---
name: test_fabs_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fabs_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_FABS %0
...

25
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir Normal file
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@ -0,0 +1,25 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
---
name: test_fneg_f32
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fneg_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FNEG %0
...
---
name: test_fneg_f64
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: test_fneg_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = G_FNEG %0
...

36
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir Normal file
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@ -0,0 +1,36 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck %s
---
name: test_fsub_f32
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: test_fsub_f32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
; CHECK: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]]
; CHECK: $vgpr0 = COPY [[FSUB]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_FSUB %0, %1
$vgpr0 = COPY %2
...
---
name: test_fsub_f64
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; CHECK-LABEL: name: test_fsub_f64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3
; CHECK: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY1]]
; CHECK: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[FNEG]]
; CHECK: $vgpr0_vgpr1 = COPY [[FADD]](s64)
%0:_(s64) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s64) = G_FSUB %0, %1
$vgpr0_vgpr1 = COPY %2
...

35
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir Normal file
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@ -0,0 +1,35 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fabs_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fabs_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[FABS:%[0-9]+]]:sgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...
---
name: fabs_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fabs_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[FABS:%[0-9]+]]:vgpr(s32) = G_FABS [[COPY]]
; CHECK: $vgpr0 = COPY [[FABS]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FABS %0
$vgpr0 = COPY %1
...

35
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir Normal file
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@ -0,0 +1,35 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
---
name: fneg_s
legalized: true
body: |
bb.0:
liveins: $sgpr0_sgpr1
; CHECK-LABEL: name: fneg_s
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[FNEG:%[0-9]+]]:sgpr(s32) = G_FNEG [[COPY]]
; CHECK: $vgpr0 = COPY [[FNEG]](s32)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = G_FNEG %0
$vgpr0 = COPY %1
...
---
name: fneg_v
legalized: true
body: |
bb.0:
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: fneg_v
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[FNEG:%[0-9]+]]:vgpr(s32) = G_FNEG [[COPY]]
; CHECK: $vgpr0 = COPY [[FNEG]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = G_FNEG %0
$vgpr0 = COPY %1
...