forked from OSchip/llvm-project
[RISCV] move `isFaultFirstLoad` into `RISCVInstrInfo`
Fix build errors in D126794 ``` ld.lld: error: undefined symbol: llvm::MachineInstr::getNumExplicitDefs() const >>> referenced by RISCVBaseInfo.cpp >>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a ld.lld: error: undefined symbol: llvm::MachineInstr::findRegisterDefOperandIdx(llvm::Register, bool, bool, llvm::TargetRegisterInfo const*) const >>> referenced by RISCVBaseInfo.cpp >>> RISCVBaseInfo.cpp.o:(llvm::isFaultFirstLoad(llvm::MachineInstr const&)) in archive lib/libLLVMRISCVDesc.a clang-15: error: linker command failed with exit code 1 (use -v to see invocation) ``` Reviewed By: fakepaper56 Differential Revision: https://reviews.llvm.org/D127477
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@ -182,9 +182,4 @@ void RISCVVType::printVType(unsigned VType, raw_ostream &OS) {
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OS << ", mu";
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}
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bool isFaultFirstLoad(const MachineInstr &MI) {
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return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
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!MI.isInlineAsm();
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}
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} // namespace llvm
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@ -433,7 +433,13 @@ void printVType(unsigned VType, raw_ostream &OS);
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} // namespace RISCVVType
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bool isFaultFirstLoad(const MachineInstr &MI);
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namespace RISCVVInstInfo {
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inline static bool isFaultFirstLoad(const MachineInstr &MI) {
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return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) &&
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!MI.isInlineAsm();
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}
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} // namespace RISCVVInstInfo
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} // namespace llvm
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#endif
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@ -1414,7 +1414,7 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) {
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void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
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for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
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MachineInstr &MI = *I++;
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if (isFaultFirstLoad(MI)) {
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if (RISCVVInstInfo::isFaultFirstLoad(MI)) {
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Register VLOutput = MI.getOperand(1).getReg();
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if (!MRI->use_nodbg_empty(VLOutput))
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BuildMI(MBB, I, MI.getDebugLoc(), TII->get(RISCV::PseudoReadVL),
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@ -158,7 +158,7 @@ static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
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if (RISCVII::hasSEWOp(TSFlags))
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--NumOps;
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bool hasVLOutput = isFaultFirstLoad(*MI);
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bool hasVLOutput = RISCVVInstInfo::isFaultFirstLoad(*MI);
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for (unsigned OpNo = 0; OpNo != NumOps; ++OpNo) {
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const MachineOperand &MO = MI->getOperand(OpNo);
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// Skip vl ouput. It should be the second output.
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