forked from OSchip/llvm-project
[x86] enable machine combiner reassociations for 128-bit vector single/double adds
llvm-svn: 244403
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df005cbe19
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e0178262d4
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@ -6371,8 +6371,12 @@ static bool isAssociativeAndCommutative(const MachineInstr &Inst) {
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case X86::IMUL32rr:
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case X86::IMUL64rr:
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return true;
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case X86::ADDPDrr:
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case X86::ADDPSrr:
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case X86::ADDSDrr:
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case X86::ADDSSrr:
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case X86::VADDPDrr:
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case X86::VADDPSrr:
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case X86::VADDSDrr:
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case X86::VADDSSrr:
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case X86::MULSDrr:
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@ -210,3 +210,47 @@ define double @reassociate_muls_double(double %x0, double %x1, double %x2, doubl
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ret double %t2
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}
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; Verify that SSE and AVX 128-bit vector single-precison adds are reassociated.
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define <4 x float> @reassociate_adds_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
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; SSE-LABEL: reassociate_adds_v4f32:
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; SSE: # BB#0:
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; SSE-NEXT: mulps %xmm1, %xmm0
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; SSE-NEXT: addps %xmm3, %xmm2
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; SSE-NEXT: addps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: reassociate_adds_v4f32:
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; AVX: # BB#0:
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; AVX-NEXT: vmulps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vaddps %xmm3, %xmm2, %xmm1
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; AVX-NEXT: vaddps %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%t0 = fmul <4 x float> %x0, %x1
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%t1 = fadd <4 x float> %x2, %t0
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%t2 = fadd <4 x float> %x3, %t1
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ret <4 x float> %t2
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}
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; Verify that SSE and AVX 128-bit vector double-precison adds are reassociated.
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define <2 x double> @reassociate_adds_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
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; SSE-LABEL: reassociate_adds_v2f64:
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; SSE: # BB#0:
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; SSE-NEXT: mulpd %xmm1, %xmm0
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; SSE-NEXT: addpd %xmm3, %xmm2
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; SSE-NEXT: addpd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: reassociate_adds_v2f64:
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; AVX: # BB#0:
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; AVX-NEXT: vmulpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: vaddpd %xmm3, %xmm2, %xmm1
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; AVX-NEXT: vaddpd %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%t0 = fmul <2 x double> %x0, %x1
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%t1 = fadd <2 x double> %x2, %t0
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%t2 = fadd <2 x double> %x3, %t1
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ret <2 x double> %t2
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}
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