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Simplify lowering and selection of exception ops. 

llvm-svn: 34488
This commit is contained in:
Jim Laskey 2007-02-22 14:56:36 +00:00
parent 20525d2836
commit e0008e23cf
7 changed files with 15 additions and 57 deletions
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8
llvm/include/llvm/Target/MRegisterInfo.h
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@ -470,14 +470,6 @@ public:
/// address can be found.
virtual unsigned getRARegister() const = 0;
/// getEHExceptionRegister - This method should return the register containing
/// the address of the exception info on entry to a landing pad.
virtual unsigned getEHExceptionRegister() const = 0;
/// getEHHandlerRegister - This method should return the register containing
/// the switch table selection on entry to an landing pad.
virtual unsigned getEHHandlerRegister() const = 0;
/// getLocation - This method should return the actual location of a frame
/// variable given the frame index. The location is returned in ML.
/// Subclasses should override this method for special handling of frame

3
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -1190,9 +1190,6 @@ SDOperand ARMTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return LowerFORMAL_ARGUMENTS(Op, DAG);
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
// Exception address and exception selector. Currently unimplemented.
case ISD::EXCEPTIONADDR: break;
case ISD::EHSELECTION: break;
}
return SDOperand();
}

3
llvm/lib/Target/Alpha/AlphaISelLowering.cpp
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@ -548,9 +548,6 @@ SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
return DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64);
//FIXME: implement
case ISD::FRAMEADDR: break;
// Exception address and exception selector. Currently unimplemented.
case ISD::EXCEPTIONADDR: break;
case ISD::EHSELECTION: break;
}
return SDOperand();

3
llvm/lib/Target/IA64/IA64ISelLowering.cpp
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@ -590,9 +590,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
// Exception address and exception selector. Currently unimplemented.
case ISD::EXCEPTIONADDR: break;
case ISD::EHSELECTION: break;
}
return SDOperand();
}

47
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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@ -141,13 +141,17 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
// Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// FIXME - use subtarget debug flags
if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
setOperationAction(ISD::LABEL, MVT::Other, Expand);
} else {
setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
}
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
@ -283,10 +287,15 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setShiftAmountType(MVT::i32);
setSetCCResultContents(ZeroOrOneSetCCResult);
if (TM.getSubtarget<PPCSubtarget>().isPPC64())
if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
setStackPointerRegisterToSaveRestore(PPC::X1);
else
setExceptionPointerRegister(PPC::X3);
setExceptionSelectorRegister(PPC::X4);
} else {
setStackPointerRegisterToSaveRestore(PPC::R1);
setExceptionPointerRegister(PPC::R3);
setExceptionSelectorRegister(PPC::R4);
}
// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::SINT_TO_FP);
@ -2610,30 +2619,6 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
}
}
/// LowerEXCEPTIONADDR - Replace EXCEPTIONADDR with a copy from the exception
/// register. The register was made live in the ISel.
static SDOperand LowerEXCEPTIONADDR(SDOperand Op, SelectionDAG &DAG) {
const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
getTargetMachine().
getRegisterInfo();
MVT::ValueType VT = Op.Val->getValueType(0);
unsigned Reg = MRI->getEHExceptionRegister();
SDOperand Result = DAG.getCopyFromReg(Op.getOperand(0), Reg, VT);
return Result.getValue(Op.ResNo);
}
/// LowerEXCEPTIONADDR - Replace EHSELECTION with a copy from the exception
/// selection register. The register was made live in the ISel.
static SDOperand LowerEHSELECTION(SDOperand Op, SelectionDAG &DAG) {
const MRegisterInfo *MRI = DAG.getTargetLoweringInfo().
getTargetMachine().
getRegisterInfo();
MVT::ValueType VT = Op.Val->getValueType(0);
unsigned Reg = MRI->getEHHandlerRegister();
SDOperand Result = DAG.getCopyFromReg(Op.getOperand(1), Reg, VT);
return Result.getValue(Op.ResNo);
}
/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
@ -2671,10 +2656,6 @@ SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
// Exception address and exception selector.
case ISD::EXCEPTIONADDR: return LowerEXCEPTIONADDR(Op, DAG);
case ISD::EHSELECTION: return LowerEHSELECTION(Op, DAG);
}
return SDOperand();
}

3
llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
View File

@ -871,9 +871,6 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
// Frame & Return address. Currently unimplemented
case ISD::RETURNADDR: break;
case ISD::FRAMEADDR: break;
// Exception address and exception selector. Currently unimplemented.
case ISD::EXCEPTIONADDR: break;
case ISD::EHSELECTION: break;
}
return SDOperand();
}

3
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -4675,9 +4675,6 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
// Exception address and exception selector. Currently unimplemented.
case ISD::EXCEPTIONADDR: break;
case ISD::EHSELECTION: break;
}
return SDOperand();
}