forked from OSchip/llvm-project
[X86][Btver2] Add ResourceCycles and NumMicroOps overrides to scalar instructions. NFCI.
Currently still use default values - this is setup for a future patch. llvm-svn: 327582
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@ -76,14 +76,20 @@ def : ReadAdvance<ReadAfterLd, 3>;
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// folded loads.
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multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat> {
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int Lat, int Res = 1, int UOps = 1> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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def : WriteRes<SchedRW, [ExePort]> {
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let Latency = Lat;
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let ResourceCycles = [Res];
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let NumMicroOps = UOps;
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}
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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let Latency = !add(Lat, 3);
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let ResourceCycles = [1, Res];
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let NumMicroOps = UOps;
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}
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}
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