forked from OSchip/llvm-project
[NFC][LSR] Autogenerate check lines in tests being affected by upcoming patch
This commit is contained in:
Roman Lebedev
parent
b3d2df42f7
commit
dfdfcdc8d3
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@ -1,3 +1,4 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-reduce -S < %s | FileCheck %s
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;
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; Test LSR's use of SplitCriticalEdge during phi rewriting.
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@ -7,13 +8,40 @@ target triple = "x86_64-apple-darwin"
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; Provide legal integer types.
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target datalayout = "n8:16:32:64"
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; Verify that identical edges are merged. rdar://problem/6453893
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; CHECK-LABEL: @test1(
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; CHECK: bb89:
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; CHECK: phi i8* [ %lsr.iv.next1, %bbA.bb89_crit_edge ], [ %lsr.iv.next1, %bbB.bb89_crit_edge ]{{$}}
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define i8* @test1() {
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;
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; CHECK-LABEL: @test1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
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; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i8*
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; CHECK-NEXT: br i1 false, label [[LOOP]], label [[LOOPEXIT:%.*]]
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; CHECK: loopexit:
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; CHECK-NEXT: br i1 false, label [[BBA:%.*]], label [[BBB:%.*]]
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; CHECK: bbA:
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; CHECK-NEXT: switch i32 0, label [[BBA_BB89_CRIT_EDGE:%.*]] [
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; CHECK-NEXT: i32 47, label [[BBA_BB89_CRIT_EDGE]]
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; CHECK-NEXT: i32 58, label [[BBA_BB89_CRIT_EDGE]]
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; CHECK-NEXT: ]
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; CHECK: bbA.bb89_crit_edge:
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; CHECK-NEXT: br label [[BB89:%.*]]
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; CHECK: bbB:
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; CHECK-NEXT: switch i8 0, label [[BBB_BB89_CRIT_EDGE:%.*]] [
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; CHECK-NEXT: i8 47, label [[BBB_BB89_CRIT_EDGE]]
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; CHECK-NEXT: i8 58, label [[BBB_BB89_CRIT_EDGE]]
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; CHECK-NEXT: ]
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; CHECK: bbB.bb89_crit_edge:
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; CHECK-NEXT: br label [[BB89]]
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; CHECK: bb89:
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; CHECK-NEXT: [[TMP75PHI:%.*]] = phi i8* [ [[LSR_IV_NEXT1]], [[BBA_BB89_CRIT_EDGE]] ], [ [[LSR_IV_NEXT1]], [[BBB_BB89_CRIT_EDGE]] ]
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i8* [[TMP75PHI]]
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;
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entry:
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br label %loop
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@ -28,14 +56,14 @@ loopexit:
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bbA:
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switch i32 0, label %bb89 [
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i32 47, label %bb89
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i32 58, label %bb89
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i32 47, label %bb89
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i32 58, label %bb89
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]
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bbB:
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switch i8 0, label %bb89 [
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i8 47, label %bb89
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i8 58, label %bb89
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i8 47, label %bb89
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i8 58, label %bb89
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]
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bb89:
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@ -47,10 +75,37 @@ exit:
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}
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; Handle single-predecessor phis: PR13756
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; CHECK-LABEL: @test2(
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; CHECK: bb89:
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; CHECK: phi i8* [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ], [ %lsr.iv.next1, %bbA ]{{$}}
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define i8* @test2() {
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;
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; CHECK-LABEL: @test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[LOOP]] ], [ 0, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add nuw nsw i64 [[LSR_IV]], 1
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; CHECK-NEXT: [[LSR_IV_NEXT1:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i8*
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; CHECK-NEXT: br i1 false, label [[LOOP]], label [[LOOPEXIT:%.*]]
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; CHECK: loopexit:
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; CHECK-NEXT: br i1 false, label [[BBA:%.*]], label [[BBB:%.*]]
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; CHECK: bbA:
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; CHECK-NEXT: switch i32 0, label [[BB89:%.*]] [
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; CHECK-NEXT: i32 47, label [[BB89]]
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; CHECK-NEXT: i32 58, label [[BB89]]
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; CHECK-NEXT: ]
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; CHECK: bbB:
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; CHECK-NEXT: switch i8 0, label [[BBB_EXIT_CRIT_EDGE:%.*]] [
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; CHECK-NEXT: i8 47, label [[BBB_EXIT_CRIT_EDGE]]
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; CHECK-NEXT: i8 58, label [[BBB_EXIT_CRIT_EDGE]]
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; CHECK-NEXT: ]
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; CHECK: bbB.exit_crit_edge:
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; CHECK-NEXT: br label [[EXIT:%.*]]
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; CHECK: bb89:
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; CHECK-NEXT: [[TMP75PHI:%.*]] = phi i8* [ [[LSR_IV_NEXT1]], [[BBA]] ], [ [[LSR_IV_NEXT1]], [[BBA]] ], [ [[LSR_IV_NEXT1]], [[BBA]] ]
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: [[RESULT:%.*]] = phi i8* [ [[TMP75PHI]], [[BB89]] ], [ [[LSR_IV_NEXT1]], [[BBB_EXIT_CRIT_EDGE]] ]
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; CHECK-NEXT: ret i8* [[RESULT]]
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;
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entry:
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br label %loop
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@ -65,14 +120,14 @@ loopexit:
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bbA:
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switch i32 0, label %bb89 [
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i32 47, label %bb89
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i32 58, label %bb89
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i32 47, label %bb89
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i32 58, label %bb89
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]
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bbB:
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switch i8 0, label %exit [
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i8 47, label %exit
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i8 58, label %exit
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i8 47, label %exit
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i8 58, label %exit
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]
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bb89:
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@ -1,21 +1,10 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -loop-reduce -S < %s | FileCheck %s
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; PR9939
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; LSR should properly handle the post-inc offset when folding the
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; non-IV operand of an icmp into the IV.
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; CHECK: [[r1:%[a-z0-9\.]+]] = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast
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; CHECK: [[r2:%[a-z0-9\.]+]] = lshr exact i64 [[r1]], 1
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; CHECK: [[r3:%[a-z0-9\.]+]] = bitcast i64 [[r2]] to i64
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; CHECK: for.body.lr.ph:
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; CHECK: [[r4:%[a-z0-9]+]] = shl nuw i64 [[r3]], 1
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; CHECK: br label %for.body
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; CHECK: for.body:
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; CHECK: %lsr.iv2 = phi i64 [ %lsr.iv.next, %for.body ], [ [[r4]], %for.body.lr.ph ]
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; CHECK: %lsr.iv.next = add i64 %lsr.iv2, -2
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; CHECK: %lsr.iv.next3 = inttoptr i64 %lsr.iv.next to i16*
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; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next3, null
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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%struct.Vector2 = type { i16*, [64 x i16], i32 }
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@ -23,6 +12,77 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
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@.str = private unnamed_addr constant [37 x i8] c"0123456789abcdefghijklmnopqrstuvwxyz\00"
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define void @_Z15IntegerToStringjjR7Vector2(i32 %i, i32 %radix, %struct.Vector2* nocapture %result) nounwind noinline {
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; CHECK-LABEL: @_Z15IntegerToStringjjR7Vector2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[BUFFER:%.*]] = alloca [33 x i16], align 16
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; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds [33 x i16], [33 x i16]* [[BUFFER]], i64 0, i64 33
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; CHECK-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i16* [[ADD_PTR]] to i64
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; CHECK-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i16* [[ADD_PTR]] to i64
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; CHECK-NEXT: [[SCEVGEP4:%.*]] = getelementptr [33 x i16], [33 x i16]* [[BUFFER]], i64 0, i64 32
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; CHECK-NEXT: [[SCEVGEP45:%.*]] = bitcast i16* [[SCEVGEP4]] to [33 x i16]*
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; CHECK-NEXT: [[SCEVGEP11:%.*]] = getelementptr [33 x i16], [33 x i16]* [[BUFFER]], i64 1, i64 0
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; CHECK-NEXT: [[SCEVGEP1112:%.*]] = bitcast i16* [[SCEVGEP11]] to [33 x i16]*
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; CHECK-NEXT: br label [[DO_BODY:%.*]]
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; CHECK: do.body:
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; CHECK-NEXT: [[LSR_IV15:%.*]] = phi i64 [ [[LSR_IV_NEXT16:%.*]], [[DO_BODY]] ], [ -1, [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[LSR_IV13:%.*]] = phi [33 x i16]* [ [[TMP2:%.*]], [[DO_BODY]] ], [ [[SCEVGEP1112]], [[ENTRY]] ]
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; CHECK-NEXT: [[LSR_IV6:%.*]] = phi [33 x i16]* [ [[TMP1:%.*]], [[DO_BODY]] ], [ [[SCEVGEP45]], [[ENTRY]] ]
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; CHECK-NEXT: [[I_ADDR_0:%.*]] = phi i32 [ [[DIV:%.*]], [[DO_BODY]] ], [ [[I:%.*]], [[ENTRY]] ]
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; CHECK-NEXT: [[LSR_IV617:%.*]] = bitcast [33 x i16]* [[LSR_IV6]] to i16*
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; CHECK-NEXT: [[REM:%.*]] = urem i32 [[I_ADDR_0]], 10
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; CHECK-NEXT: [[DIV]] = udiv i32 [[I_ADDR_0]], 10
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; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[REM]] to i64
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [37 x i8], [37 x i8]* @.str, i64 0, i64 [[IDXPROM]]
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; CHECK-NEXT: [[TMP5:%.*]] = load i8, i8* [[ARRAYIDX]], align 1
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; CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP5]] to i16
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; CHECK-NEXT: store i16 [[CONV]], i16* [[LSR_IV617]], align 2
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; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[I_ADDR_0]], 9
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; CHECK-NEXT: [[SCEVGEP7:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV6]], i64 0, i64 -1
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; CHECK-NEXT: [[TMP1]] = bitcast i16* [[SCEVGEP7]] to [33 x i16]*
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; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV13]], i64 0, i64 -1
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; CHECK-NEXT: [[TMP2]] = bitcast i16* [[SCEVGEP14]] to [33 x i16]*
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; CHECK-NEXT: [[LSR_IV_NEXT16]] = add i64 [[LSR_IV15]], 1
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; CHECK-NEXT: br i1 [[TMP0]], label [[DO_BODY]], label [[DO_END:%.*]]
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; CHECK: do.end:
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; CHECK-NEXT: [[XAP_0:%.*]] = inttoptr i64 [[LSR_IV_NEXT16]] to i1*
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; CHECK-NEXT: [[CAP_0:%.*]] = ptrtoint i1* [[XAP_0]] to i64
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; CHECK-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]]
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; CHECK-NEXT: [[SUB_PTR_DIV39:%.*]] = lshr exact i64 [[SUB_PTR_SUB]], 1
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; CHECK-NEXT: [[CONV11:%.*]] = trunc i64 [[SUB_PTR_DIV39]] to i32
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; CHECK-NEXT: [[MLENGTH:%.*]] = getelementptr inbounds [[STRUCT_VECTOR2:%.*]], %struct.Vector2* [[RESULT:%.*]], i64 0, i32 2
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; CHECK-NEXT: [[IDX_EXT21:%.*]] = bitcast i64 [[SUB_PTR_DIV39]] to i64
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; CHECK-NEXT: [[CMP2740:%.*]] = icmp eq i64 [[IDX_EXT21]], 0
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; CHECK-NEXT: br i1 [[CMP2740]], label [[FOR_END:%.*]], label [[FOR_BODY_LR_PH:%.*]]
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; CHECK: for.body.lr.ph:
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; CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[MLENGTH]], align 4
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; CHECK-NEXT: [[MBEGIN:%.*]] = getelementptr inbounds [[STRUCT_VECTOR2]], %struct.Vector2* [[RESULT]], i64 0, i32 0
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; CHECK-NEXT: [[TMP14:%.*]] = load i16*, i16** [[MBEGIN]], align 8
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; CHECK-NEXT: [[TMP48:%.*]] = zext i32 [[TMP16]] to i64
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; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i16, i16* [[TMP14]], i64 [[TMP48]]
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; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i64 [[IDX_EXT21]], 1
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; CHECK-NEXT: br label [[FOR_BODY:%.*]]
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; CHECK: for.body:
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; CHECK-NEXT: [[LSR_IV8:%.*]] = phi [33 x i16]* [ [[TMP4:%.*]], [[FOR_BODY]] ], [ [[TMP2]], [[FOR_BODY_LR_PH]] ]
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; CHECK-NEXT: [[LSR_IV2:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[FOR_BODY]] ], [ [[TMP3]], [[FOR_BODY_LR_PH]] ]
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i16* [ [[SCEVGEP1:%.*]], [[FOR_BODY]] ], [ [[SCEVGEP]], [[FOR_BODY_LR_PH]] ]
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; CHECK-NEXT: [[LSR_IV810:%.*]] = bitcast [33 x i16]* [[LSR_IV8]] to i16*
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; CHECK-NEXT: [[TMP29:%.*]] = load i16, i16* [[LSR_IV810]], align 2
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; CHECK-NEXT: store i16 [[TMP29]], i16* [[LSR_IV]], align 2
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; CHECK-NEXT: [[SCEVGEP1]] = getelementptr i16, i16* [[LSR_IV]], i64 1
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV2]], -2
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; CHECK-NEXT: [[LSR_IV_NEXT3:%.*]] = inttoptr i64 [[LSR_IV_NEXT]] to i16*
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; CHECK-NEXT: [[SCEVGEP9:%.*]] = getelementptr [33 x i16], [33 x i16]* [[LSR_IV8]], i64 0, i64 1
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; CHECK-NEXT: [[TMP4]] = bitcast i16* [[SCEVGEP9]] to [33 x i16]*
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; CHECK-NEXT: [[CMP27:%.*]] = icmp eq i16* [[LSR_IV_NEXT3]], null
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; CHECK-NEXT: br i1 [[CMP27]], label [[FOR_END_LOOPEXIT:%.*]], label [[FOR_BODY]]
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; CHECK: for.end.loopexit:
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; CHECK-NEXT: br label [[FOR_END]]
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; CHECK: for.end:
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; CHECK-NEXT: [[TMP38:%.*]] = load i32, i32* [[MLENGTH]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP38]], [[CONV11]]
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; CHECK-NEXT: store i32 [[ADD]], i32* [[MLENGTH]], align 4
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; CHECK-NEXT: ret void
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;
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entry:
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%buffer = alloca [33 x i16], align 16
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%add.ptr = getelementptr inbounds [33 x i16], [33 x i16]* %buffer, i64 0, i64 33
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