forked from OSchip/llvm-project
revert r251849; need to move tests to arch-specific folders
llvm-svn: 251851
This commit is contained in:
Sanjay Patel
parent
cf2ed26836
commit
dfc825eb36
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@ -175,7 +175,6 @@ class TypePromotionTransaction;
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bool optimizeExtUses(Instruction *I);
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bool optimizeSelectInst(SelectInst *SI);
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bool optimizeShuffleVectorInst(ShuffleVectorInst *SI);
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bool optimizeSwitchInst(SwitchInst *CI);
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bool optimizeExtractElementInst(Instruction *Inst);
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bool dupRetToEnableTailCallOpts(BasicBlock *BB);
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bool placeDbgValues(Function &F);
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@ -4400,49 +4399,6 @@ bool CodeGenPrepare::optimizeShuffleVectorInst(ShuffleVectorInst *SVI) {
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return MadeChange;
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}
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bool CodeGenPrepare::optimizeSwitchInst(SwitchInst *SI) {
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if (!TLI || !DL)
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return false;
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Value *Cond = SI->getCondition();
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Type *OldType = Cond->getType();
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LLVMContext &Context = Cond->getContext();
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MVT RegType = TLI->getRegisterType(Context, TLI->getValueType(*DL, OldType));
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unsigned RegWidth = RegType.getSizeInBits();
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if (RegWidth <= cast<IntegerType>(OldType)->getBitWidth())
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return false;
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// If the register width is greater than the type width, expand the condition
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// of the switch instruction and each case constant to the width of the
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// register. By widening the type of the switch condition, subsequent
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// comparisons (for case comparisons) will not need to be extended to the
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// preferred register width, so we will potentially eliminate N-1 extends,
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// where N is the number of cases in the switch.
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auto *NewType = Type::getIntNTy(Context, RegWidth);
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// Zero-extend the switch condition and case constants unless the switch
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// condition is a function argument that is already being sign-extended.
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// In that case, we can avoid an unnecessary mask/extension by sign-extending
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// everything instead.
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Instruction::CastOps ExtType = Instruction::ZExt;
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if (auto *Arg = dyn_cast<Argument>(Cond))
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if (Arg->hasSExtAttr())
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ExtType = Instruction::SExt;
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auto *ExtInst = CastInst::Create(ExtType, Cond, NewType);
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ExtInst->insertBefore(SI);
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SI->setCondition(ExtInst);
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for (SwitchInst::CaseIt Case : SI->cases()) {
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APInt NarrowConst = Case.getCaseValue()->getValue();
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APInt WideConst = (ExtType == Instruction::ZExt) ?
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NarrowConst.zext(RegWidth) : NarrowConst.sext(RegWidth);
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Case.setValue(ConstantInt::get(Context, WideConst));
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}
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return true;
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}
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namespace {
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/// \brief Helper class to promote a scalar operation to a vector one.
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/// This class is used to move downward extractelement transition.
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@ -4915,9 +4871,6 @@ bool CodeGenPrepare::optimizeInst(Instruction *I, bool& ModifiedDT) {
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if (ShuffleVectorInst *SVI = dyn_cast<ShuffleVectorInst>(I))
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return optimizeShuffleVectorInst(SVI);
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if (auto *Switch = dyn_cast<SwitchInst>(I))
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return optimizeSwitchInst(Switch);
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if (isa<ExtractElementInst>(I))
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return optimizeExtractElementInst(I);
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@ -1,107 +0,0 @@
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;; PowerPC is arbitralily chosen as a 32/64-bit RISC representative to show the transform in all tests.
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;; x86 is chosen to show that the transform may differ when 8-bit and 16-bit registers are available.
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; RUN: opt < %s -codegenprepare -S -mtriple=powerpc64-unknown-unknown | FileCheck %s --check-prefix=PPC --check-prefix=ALL
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; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X86 --check-prefix=ALL
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; PPC widens to 32-bit; no change for x86 because 16-bit registers are part of the architecture.
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define i32 @widen_switch_i16(i32 %a) {
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entry:
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%trunc = trunc i32 %a to i16
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switch i16 %trunc, label %sw.default [
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i16 1, label %sw.bb0
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i16 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ALL-LABEL: @widen_switch_i16(
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; PPC: %0 = zext i16 %trunc to i32
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; PPC-NEXT: switch i32 %0, label %sw.default [
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; PPC-NEXT: i32 1, label %return
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; PPC-NEXT: i32 65535, label %sw.bb1
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;
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; X86: %trunc = trunc i32 %a to i16
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; X86-NEXT: switch i16 %trunc, label %sw.default [
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; X86-NEXT: i16 1, label %return
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; X86-NEXT: i16 -1, label %sw.bb1
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}
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; Both architectures widen to 32-bit from a smaller, non-native type.
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define i32 @widen_switch_i17(i32 %a) {
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entry:
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%trunc = trunc i32 %a to i17
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switch i17 %trunc, label %sw.default [
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i17 10, label %sw.bb0
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i17 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ALL-LABEL: @widen_switch_i17(
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; ALL: %0 = zext i17 %trunc to i32
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; ALL-NEXT: switch i32 %0, label %sw.default [
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; ALL-NEXT: i32 10, label %return
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; ALL-NEXT: i32 131071, label %sw.bb1
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}
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; If the switch condition is a sign-extended function argument, then the
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; condition and cases should be sign-extended rather than zero-extended
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; because the sign-extension can be optimized away.
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define i32 @widen_switch_i16_sext(i2 signext %a) {
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entry:
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switch i2 %a, label %sw.default [
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i2 1, label %sw.bb0
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i2 -1, label %sw.bb1
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]
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sw.bb0:
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br label %return
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sw.bb1:
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br label %return
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sw.default:
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br label %return
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return:
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%retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
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ret i32 %retval
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; ALL-LABEL: @widen_switch_i16_sext(
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; PPC: %0 = sext i2 %a to i32
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; PPC-NEXT: switch i32 %0, label %sw.default [
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; PPC-NEXT: i32 1, label %return
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; PPC-NEXT: i32 -1, label %sw.bb1
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;
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; X86: %0 = sext i2 %a to i8
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; X86-NEXT: switch i8 %0, label %sw.default [
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; X86-NEXT: i8 1, label %return
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; X86-NEXT: i8 -1, label %sw.bb1
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}
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