maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU: Propagate undef flag during pre-RA exec mask optimizations 

Summary: Issue: https://github.com/GPUOpen-Drivers/llpc/issues/204

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68184

llvm-svn: 374041
This commit is contained in:
Nicolai Haehnle 2019-10-08 12:46:32 +00:00
parent 7febdb7f27
commit df6e67697b
2 changed files with 31 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
View File

@ -250,15 +250,16 @@ static unsigned optimizeVcndVcmpPair(MachineBasicBlock &MBB,
Op1->getImm() != 0 || Op2->getImm() != 1)
return AMDGPU::NoRegister;
LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t'
<< *Cmp << '\t' << *And);
LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
<< *And);
Register CCReg = CC->getReg();
LIS->RemoveMachineInstrFromMaps(*And);
MachineInstr *Andn2 = BuildMI(MBB, *And, And->getDebugLoc(),
TII->get(Andn2Opc), And->getOperand(0).getReg())
.addReg(ExecReg)
.addReg(CCReg, 0, CC->getSubReg());
MachineInstr *Andn2 =
BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
And->getOperand(0).getReg())
.addReg(ExecReg)
.addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
And->eraseFromParent();
LIS->InsertMachineInstrInMaps(*Andn2);

25
llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
View File

@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -run-pass=si-optimize-exec-masking-pre-ra -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# Check for regression from assuming an instruction was a copy after
# dropping the opcode check.
@ -95,3 +95,26 @@ body: |
$exec = S_OR_B64 $exec, %7, implicit-def $scc
...
# When folding a v_cndmask and a v_cmp in a pattern leading to
# s_cbranch_vccz, ensure that an undef operand is handled correctly.
---
name: cndmask_cmp_cbranch_fold_undef
tracksRegLiveness: true
body: |
; GCN-LABEL: name: cndmask_cmp_cbranch_fold_undef
; GCN: bb.0:
; GCN: successors: %bb.1(0x80000000)
; GCN: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def $scc
; GCN: S_CBRANCH_VCCZ %bb.1, implicit $vcc
; GCN: bb.1:
bb.0:
%1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0:sreg_64_xexec, implicit $exec
V_CMP_NE_U32_e32 1, %1, implicit-def $vcc, implicit $exec
$vcc = S_AND_B64 $exec, $vcc, implicit-def dead $scc
S_CBRANCH_VCCZ %bb.1, implicit $vcc
bb.1:
...