forked from OSchip/llvm-project
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6e792f9ff8
commit
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@ -290,15 +290,15 @@ def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
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[(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
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VSPLT_shuffle_mask:$UIMM))]>;
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def VSPLTISB : VXForm_1<780, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisb $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
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def VSPLTISH : VXForm_1<844, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltish $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
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def VSPLTISW : VXForm_1<908, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisw $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
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def VSPLTISB : VXForm_3<780, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisb $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisb:$SIMM))]>;
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def VSPLTISH : VXForm_3<844, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltish $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltish:$SIMM))]>;
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def VSPLTISW : VXForm_3<908, (ops VRRC:$vD, s5imm:$SIMM),
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"vspltisw $vD, $SIMM", VecPerm,
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[(set VRRC:$vD, (v4f32 vecspltisw:$SIMM))]>;
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// Altivec Comparisons.
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@ -663,6 +663,21 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr,
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let Inst{21-31} = xo;
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}
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class VXForm_3<bits<11> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OL, asmstr, itin> {
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bits<5> VD;
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bits<5> IMM;
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let Pattern = pattern;
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let Inst{6-10} = VD;
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let Inst{11-15} = IMM;
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let Inst{16-20} = 0;
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let Inst{21-31} = xo;
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}
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// E-4 VXR-Form
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class VXRForm_1<bits<10> xo, dag OL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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