forked from OSchip/llvm-project
Break some dependencies in lldbUtility.
Differential Revision: https://reviews.llvm.org/D29359 llvm-svn: 293806
This commit is contained in:
Zachary Turner
parent
5569c0b953
commit
df44988b87
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@ -1,21 +0,0 @@
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//===-- ConvertEnum.h -------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLDB_UTILITY_CONVERTENUM_H
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#define LLDB_UTILITY_CONVERTENUM_H
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#include "lldb/lldb-enumerations.h"
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#include "lldb/lldb-private-enumerations.h"
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namespace lldb_private {
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const char *GetVoteAsCString(Vote vote);
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const char *GetSectionTypeAsCString(lldb::SectionType sect_type);
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}
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#endif
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@ -1,86 +0,0 @@
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//===-- PriorityPointerPair.h ----------------------------------------*- C++
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//-*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef liblldb_PriorityPointerPair_h_
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#define liblldb_PriorityPointerPair_h_
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#include "lldb/Utility/SharingPtr.h"
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#include "lldb/lldb-public.h"
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namespace lldb_utility {
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//----------------------------------------------------------------------
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// A prioritized pair of SharedPtr<T>. One of the two pointers is high
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// priority, the other is low priority.
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// The Get() method always returns high, if *high != NULL,
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// otherwise, low is returned (even if *low == NULL)
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//----------------------------------------------------------------------
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template <typename T> class PriorityPointerPair {
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public:
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typedef T &reference_type;
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typedef T *pointer_type;
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typedef typename std::shared_ptr<T> T_SP;
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PriorityPointerPair() : m_high(), m_low() {}
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PriorityPointerPair(pointer_type high, pointer_type low)
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: m_high(high), m_low(low) {}
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PriorityPointerPair(pointer_type low) : m_high(), m_low(low) {}
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PriorityPointerPair(T_SP &high, T_SP &low) : m_high(high), m_low(low) {}
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PriorityPointerPair(T_SP &low) : m_high(), m_low(low) {}
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void SwapLow(pointer_type l) { m_low.swap(l); }
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void SwapHigh(pointer_type h) { m_high.swap(h); }
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void SwapLow(T_SP l) { m_low.swap(l); }
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void SwapHigh(T_SP h) { m_high.swap(h); }
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T_SP GetLow() { return m_low; }
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T_SP GetHigh() { return m_high; }
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T_SP Get() {
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if (m_high.get())
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return m_high;
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return m_low;
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}
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void ResetHigh() { m_high.reset(); }
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void ResetLow() { m_low.reset(); }
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void Reset() {
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ResetLow();
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ResetHigh();
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}
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reference_type operator*() const { return Get().operator*(); }
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pointer_type operator->() const { return Get().operator->(); }
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~PriorityPointerPair();
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private:
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T_SP m_high;
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T_SP m_low;
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DISALLOW_COPY_AND_ASSIGN(PriorityPointerPair);
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};
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} // namespace lldb_utility
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#endif // #ifndef liblldb_PriorityPointerPair_h_
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@ -1,22 +0,0 @@
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//===-- Utils.h -------------------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef utility_Utils_h_
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#define utility_Utils_h_
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// These utilities have llvm namespace.
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#include "llvm/ADT/STLExtras.h"
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namespace lldb_private {
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// Add lldb utilities here.
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} // namespace lldb_private
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#endif // utility_Utils
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@ -10,6 +10,10 @@
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#ifndef LLDB_lldb_private_enumerations_h_
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#define LLDB_lldb_private_enumerations_h_
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/FormatProviders.h"
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#include "llvm/Support/raw_ostream.h"
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namespace lldb_private {
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//----------------------------------------------------------------------
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@ -257,4 +261,21 @@ enum class CompilerContextKind {
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} // namespace lldb_private
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namespace llvm {
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template <> struct format_provider<lldb_private::Vote> {
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static void format(const lldb_private::Vote &V, llvm::raw_ostream &Stream,
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StringRef Style) {
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switch (V) {
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case lldb_private::eVoteNo:
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Stream << "no";
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case lldb_private::eVoteNoOpinion:
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Stream << "no opinion";
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case lldb_private::eVoteYes:
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Stream << "yes";
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}
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Stream << "invalid";
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}
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};
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}
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#endif // LLDB_lldb_private_enumerations_h_
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@ -27,7 +27,6 @@
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#include "lldb/Target/ExecutionContext.h"
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#include "lldb/Target/Platform.h"
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#include "lldb/Target/Process.h"
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#include "lldb/Utility/Utils.h"
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#include "llvm/ADT/SmallString.h"
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@ -12,11 +12,104 @@
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#include "lldb/Symbol/ObjectFile.h"
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#include "lldb/Target/SectionLoadList.h"
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#include "lldb/Target/Target.h"
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#include "lldb/Utility/ConvertEnum.h"
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using namespace lldb;
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using namespace lldb_private;
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static const char *GetSectionTypeAsCString(lldb::SectionType sect_type) {
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switch (sect_type) {
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case eSectionTypeInvalid:
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return "invalid";
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case eSectionTypeCode:
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return "code";
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case eSectionTypeContainer:
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return "container";
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case eSectionTypeData:
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return "data";
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case eSectionTypeDataCString:
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return "data-cstr";
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case eSectionTypeDataCStringPointers:
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return "data-cstr-ptr";
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case eSectionTypeDataSymbolAddress:
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return "data-symbol-addr";
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case eSectionTypeData4:
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return "data-4-byte";
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case eSectionTypeData8:
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return "data-8-byte";
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case eSectionTypeData16:
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return "data-16-byte";
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case eSectionTypeDataPointers:
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return "data-ptrs";
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case eSectionTypeDebug:
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return "debug";
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case eSectionTypeZeroFill:
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return "zero-fill";
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case eSectionTypeDataObjCMessageRefs:
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return "objc-message-refs";
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case eSectionTypeDataObjCCFStrings:
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return "objc-cfstrings";
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case eSectionTypeDWARFDebugAbbrev:
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return "dwarf-abbrev";
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case eSectionTypeDWARFDebugAddr:
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return "dwarf-addr";
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case eSectionTypeDWARFDebugAranges:
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return "dwarf-aranges";
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case eSectionTypeDWARFDebugFrame:
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return "dwarf-frame";
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case eSectionTypeDWARFDebugInfo:
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return "dwarf-info";
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case eSectionTypeDWARFDebugLine:
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return "dwarf-line";
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case eSectionTypeDWARFDebugLoc:
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return "dwarf-loc";
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case eSectionTypeDWARFDebugMacInfo:
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return "dwarf-macinfo";
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case eSectionTypeDWARFDebugMacro:
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return "dwarf-macro";
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case eSectionTypeDWARFDebugPubNames:
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return "dwarf-pubnames";
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case eSectionTypeDWARFDebugPubTypes:
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return "dwarf-pubtypes";
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case eSectionTypeDWARFDebugRanges:
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return "dwarf-ranges";
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case eSectionTypeDWARFDebugStr:
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return "dwarf-str";
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case eSectionTypeDWARFDebugStrOffsets:
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return "dwarf-str-offsets";
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case eSectionTypeELFSymbolTable:
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return "elf-symbol-table";
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case eSectionTypeELFDynamicSymbols:
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return "elf-dynamic-symbols";
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case eSectionTypeELFRelocationEntries:
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return "elf-relocation-entries";
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case eSectionTypeELFDynamicLinkInfo:
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return "elf-dynamic-link-info";
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case eSectionTypeDWARFAppleNames:
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return "apple-names";
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case eSectionTypeDWARFAppleTypes:
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return "apple-types";
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case eSectionTypeDWARFAppleNamespaces:
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return "apple-namespaces";
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case eSectionTypeDWARFAppleObjC:
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return "apple-objc";
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case eSectionTypeEHFrame:
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return "eh-frame";
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case eSectionTypeARMexidx:
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return "ARM.exidx";
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case eSectionTypeARMextab:
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return "ARM.extab";
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case eSectionTypeCompactUnwind:
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return "compact-unwind";
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case eSectionTypeGoSymtab:
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return "go-symtab";
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case eSectionTypeAbsoluteAddress:
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return "absolute";
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case eSectionTypeOther:
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return "regular";
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}
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return "unknown";
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}
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Section::Section(const ModuleSP &module_sp, ObjectFile *obj_file,
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user_id_t sect_id, const ConstString &name,
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SectionType sect_type, addr_t file_addr, addr_t byte_size,
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// C++ Includes
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// Other libraries and framework includes
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// Project includes
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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@ -17,7 +17,6 @@
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#include "lldb/Interpreter/CommandInterpreter.h"
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#include "lldb/Target/ExecutionContext.h"
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#include "lldb/Target/Target.h"
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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// C++ Includes
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// Other libraries and framework includes
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// Project includes
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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@ -15,7 +15,6 @@
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// Project includes
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#include "lldb/Interpreter/CommandInterpreter.h"
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#include "lldb/Target/Platform.h"
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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@ -13,7 +13,6 @@
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// C++ Includes
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// Other libraries and framework includes
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// Project includes
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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@ -17,7 +17,6 @@
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#include "lldb/Host/StringConvert.h"
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#include "lldb/Interpreter/CommandInterpreter.h"
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#include "lldb/Target/Target.h"
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#include "lldb/Utility/Utils.h"
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#include "llvm/ADT/ArrayRef.h"
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@ -17,7 +17,6 @@
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#include "lldb/DataFormatters/DataVisualization.h"
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#include "lldb/Interpreter/CommandInterpreter.h"
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#include "lldb/Target/Target.h"
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#include "lldb/Utility/Utils.h"
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using namespace lldb;
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using namespace lldb_private;
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@ -14,7 +14,6 @@
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// Other libraries and framework includes
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// Project includes
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#include "lldb/Interpreter/Args.h"
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#include "lldb/Utility/Utils.h"
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#include "lldb/lldb-enumerations.h"
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using namespace lldb;
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@ -44,6 +44,915 @@ using namespace lldb_private;
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//
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//----------------------------------------------------------------------
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static const char *GetARMDWARFRegisterName(unsigned reg_num) {
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switch (reg_num) {
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case dwarf_r0:
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return "r0";
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case dwarf_r1:
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return "r1";
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case dwarf_r2:
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return "r2";
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case dwarf_r3:
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return "r3";
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case dwarf_r4:
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return "r4";
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case dwarf_r5:
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return "r5";
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case dwarf_r6:
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return "r6";
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case dwarf_r7:
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return "r7";
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case dwarf_r8:
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return "r8";
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case dwarf_r9:
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return "r9";
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case dwarf_r10:
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return "r10";
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case dwarf_r11:
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return "r11";
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case dwarf_r12:
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return "r12";
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case dwarf_sp:
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return "sp";
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case dwarf_lr:
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return "lr";
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case dwarf_pc:
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return "pc";
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case dwarf_cpsr:
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return "cpsr";
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case dwarf_s0:
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return "s0";
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case dwarf_s1:
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return "s1";
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case dwarf_s2:
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return "s2";
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case dwarf_s3:
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return "s3";
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case dwarf_s4:
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return "s4";
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case dwarf_s5:
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return "s5";
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case dwarf_s6:
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return "s6";
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case dwarf_s7:
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return "s7";
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case dwarf_s8:
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return "s8";
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case dwarf_s9:
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return "s9";
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case dwarf_s10:
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return "s10";
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case dwarf_s11:
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return "s11";
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case dwarf_s12:
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return "s12";
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case dwarf_s13:
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return "s13";
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case dwarf_s14:
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return "s14";
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case dwarf_s15:
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return "s15";
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case dwarf_s16:
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return "s16";
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case dwarf_s17:
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return "s17";
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case dwarf_s18:
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return "s18";
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case dwarf_s19:
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return "s19";
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case dwarf_s20:
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return "s20";
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case dwarf_s21:
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return "s21";
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case dwarf_s22:
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return "s22";
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case dwarf_s23:
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return "s23";
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case dwarf_s24:
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return "s24";
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case dwarf_s25:
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return "s25";
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case dwarf_s26:
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return "s26";
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case dwarf_s27:
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return "s27";
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case dwarf_s28:
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return "s28";
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case dwarf_s29:
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return "s29";
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case dwarf_s30:
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return "s30";
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case dwarf_s31:
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return "s31";
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// FPA Registers 0-7
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case dwarf_f0:
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return "f0";
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case dwarf_f1:
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return "f1";
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case dwarf_f2:
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return "f2";
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case dwarf_f3:
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return "f3";
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case dwarf_f4:
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return "f4";
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case dwarf_f5:
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return "f5";
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case dwarf_f6:
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return "f6";
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case dwarf_f7:
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return "f7";
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// Intel wireless MMX general purpose registers 0 - 7
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// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
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case dwarf_wCGR0:
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return "wCGR0/ACC0";
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case dwarf_wCGR1:
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return "wCGR1/ACC1";
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case dwarf_wCGR2:
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return "wCGR2/ACC2";
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case dwarf_wCGR3:
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return "wCGR3/ACC3";
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case dwarf_wCGR4:
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return "wCGR4/ACC4";
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case dwarf_wCGR5:
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return "wCGR5/ACC5";
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case dwarf_wCGR6:
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return "wCGR6/ACC6";
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case dwarf_wCGR7:
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return "wCGR7/ACC7";
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// Intel wireless MMX data registers 0 - 15
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case dwarf_wR0:
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return "wR0";
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case dwarf_wR1:
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return "wR1";
|
||||
case dwarf_wR2:
|
||||
return "wR2";
|
||||
case dwarf_wR3:
|
||||
return "wR3";
|
||||
case dwarf_wR4:
|
||||
return "wR4";
|
||||
case dwarf_wR5:
|
||||
return "wR5";
|
||||
case dwarf_wR6:
|
||||
return "wR6";
|
||||
case dwarf_wR7:
|
||||
return "wR7";
|
||||
case dwarf_wR8:
|
||||
return "wR8";
|
||||
case dwarf_wR9:
|
||||
return "wR9";
|
||||
case dwarf_wR10:
|
||||
return "wR10";
|
||||
case dwarf_wR11:
|
||||
return "wR11";
|
||||
case dwarf_wR12:
|
||||
return "wR12";
|
||||
case dwarf_wR13:
|
||||
return "wR13";
|
||||
case dwarf_wR14:
|
||||
return "wR14";
|
||||
case dwarf_wR15:
|
||||
return "wR15";
|
||||
|
||||
case dwarf_spsr:
|
||||
return "spsr";
|
||||
case dwarf_spsr_fiq:
|
||||
return "spsr_fiq";
|
||||
case dwarf_spsr_irq:
|
||||
return "spsr_irq";
|
||||
case dwarf_spsr_abt:
|
||||
return "spsr_abt";
|
||||
case dwarf_spsr_und:
|
||||
return "spsr_und";
|
||||
case dwarf_spsr_svc:
|
||||
return "spsr_svc";
|
||||
|
||||
case dwarf_r8_usr:
|
||||
return "r8_usr";
|
||||
case dwarf_r9_usr:
|
||||
return "r9_usr";
|
||||
case dwarf_r10_usr:
|
||||
return "r10_usr";
|
||||
case dwarf_r11_usr:
|
||||
return "r11_usr";
|
||||
case dwarf_r12_usr:
|
||||
return "r12_usr";
|
||||
case dwarf_r13_usr:
|
||||
return "r13_usr";
|
||||
case dwarf_r14_usr:
|
||||
return "r14_usr";
|
||||
case dwarf_r8_fiq:
|
||||
return "r8_fiq";
|
||||
case dwarf_r9_fiq:
|
||||
return "r9_fiq";
|
||||
case dwarf_r10_fiq:
|
||||
return "r10_fiq";
|
||||
case dwarf_r11_fiq:
|
||||
return "r11_fiq";
|
||||
case dwarf_r12_fiq:
|
||||
return "r12_fiq";
|
||||
case dwarf_r13_fiq:
|
||||
return "r13_fiq";
|
||||
case dwarf_r14_fiq:
|
||||
return "r14_fiq";
|
||||
case dwarf_r13_irq:
|
||||
return "r13_irq";
|
||||
case dwarf_r14_irq:
|
||||
return "r14_irq";
|
||||
case dwarf_r13_abt:
|
||||
return "r13_abt";
|
||||
case dwarf_r14_abt:
|
||||
return "r14_abt";
|
||||
case dwarf_r13_und:
|
||||
return "r13_und";
|
||||
case dwarf_r14_und:
|
||||
return "r14_und";
|
||||
case dwarf_r13_svc:
|
||||
return "r13_svc";
|
||||
case dwarf_r14_svc:
|
||||
return "r14_svc";
|
||||
|
||||
// Intel wireless MMX control register in co-processor 0 - 7
|
||||
case dwarf_wC0:
|
||||
return "wC0";
|
||||
case dwarf_wC1:
|
||||
return "wC1";
|
||||
case dwarf_wC2:
|
||||
return "wC2";
|
||||
case dwarf_wC3:
|
||||
return "wC3";
|
||||
case dwarf_wC4:
|
||||
return "wC4";
|
||||
case dwarf_wC5:
|
||||
return "wC5";
|
||||
case dwarf_wC6:
|
||||
return "wC6";
|
||||
case dwarf_wC7:
|
||||
return "wC7";
|
||||
|
||||
// VFP-v3/Neon
|
||||
case dwarf_d0:
|
||||
return "d0";
|
||||
case dwarf_d1:
|
||||
return "d1";
|
||||
case dwarf_d2:
|
||||
return "d2";
|
||||
case dwarf_d3:
|
||||
return "d3";
|
||||
case dwarf_d4:
|
||||
return "d4";
|
||||
case dwarf_d5:
|
||||
return "d5";
|
||||
case dwarf_d6:
|
||||
return "d6";
|
||||
case dwarf_d7:
|
||||
return "d7";
|
||||
case dwarf_d8:
|
||||
return "d8";
|
||||
case dwarf_d9:
|
||||
return "d9";
|
||||
case dwarf_d10:
|
||||
return "d10";
|
||||
case dwarf_d11:
|
||||
return "d11";
|
||||
case dwarf_d12:
|
||||
return "d12";
|
||||
case dwarf_d13:
|
||||
return "d13";
|
||||
case dwarf_d14:
|
||||
return "d14";
|
||||
case dwarf_d15:
|
||||
return "d15";
|
||||
case dwarf_d16:
|
||||
return "d16";
|
||||
case dwarf_d17:
|
||||
return "d17";
|
||||
case dwarf_d18:
|
||||
return "d18";
|
||||
case dwarf_d19:
|
||||
return "d19";
|
||||
case dwarf_d20:
|
||||
return "d20";
|
||||
case dwarf_d21:
|
||||
return "d21";
|
||||
case dwarf_d22:
|
||||
return "d22";
|
||||
case dwarf_d23:
|
||||
return "d23";
|
||||
case dwarf_d24:
|
||||
return "d24";
|
||||
case dwarf_d25:
|
||||
return "d25";
|
||||
case dwarf_d26:
|
||||
return "d26";
|
||||
case dwarf_d27:
|
||||
return "d27";
|
||||
case dwarf_d28:
|
||||
return "d28";
|
||||
case dwarf_d29:
|
||||
return "d29";
|
||||
case dwarf_d30:
|
||||
return "d30";
|
||||
case dwarf_d31:
|
||||
return "d31";
|
||||
|
||||
// NEON 128-bit vector registers (overlays the d registers)
|
||||
case dwarf_q0:
|
||||
return "q0";
|
||||
case dwarf_q1:
|
||||
return "q1";
|
||||
case dwarf_q2:
|
||||
return "q2";
|
||||
case dwarf_q3:
|
||||
return "q3";
|
||||
case dwarf_q4:
|
||||
return "q4";
|
||||
case dwarf_q5:
|
||||
return "q5";
|
||||
case dwarf_q6:
|
||||
return "q6";
|
||||
case dwarf_q7:
|
||||
return "q7";
|
||||
case dwarf_q8:
|
||||
return "q8";
|
||||
case dwarf_q9:
|
||||
return "q9";
|
||||
case dwarf_q10:
|
||||
return "q10";
|
||||
case dwarf_q11:
|
||||
return "q11";
|
||||
case dwarf_q12:
|
||||
return "q12";
|
||||
case dwarf_q13:
|
||||
return "q13";
|
||||
case dwarf_q14:
|
||||
return "q14";
|
||||
case dwarf_q15:
|
||||
return "q15";
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo ®_info) {
|
||||
::memset(®_info, 0, sizeof(RegisterInfo));
|
||||
::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
|
||||
|
||||
if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
|
||||
reg_info.byte_size = 16;
|
||||
reg_info.format = eFormatVectorOfUInt8;
|
||||
reg_info.encoding = eEncodingVector;
|
||||
}
|
||||
|
||||
if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
|
||||
reg_info.byte_size = 8;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
|
||||
reg_info.byte_size = 4;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
|
||||
reg_info.byte_size = 12;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else {
|
||||
reg_info.byte_size = 4;
|
||||
reg_info.format = eFormatHex;
|
||||
reg_info.encoding = eEncodingUint;
|
||||
}
|
||||
|
||||
reg_info.kinds[eRegisterKindDWARF] = reg_num;
|
||||
|
||||
switch (reg_num) {
|
||||
case dwarf_r0:
|
||||
reg_info.name = "r0";
|
||||
break;
|
||||
case dwarf_r1:
|
||||
reg_info.name = "r1";
|
||||
break;
|
||||
case dwarf_r2:
|
||||
reg_info.name = "r2";
|
||||
break;
|
||||
case dwarf_r3:
|
||||
reg_info.name = "r3";
|
||||
break;
|
||||
case dwarf_r4:
|
||||
reg_info.name = "r4";
|
||||
break;
|
||||
case dwarf_r5:
|
||||
reg_info.name = "r5";
|
||||
break;
|
||||
case dwarf_r6:
|
||||
reg_info.name = "r6";
|
||||
break;
|
||||
case dwarf_r7:
|
||||
reg_info.name = "r7";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
|
||||
break;
|
||||
case dwarf_r8:
|
||||
reg_info.name = "r8";
|
||||
break;
|
||||
case dwarf_r9:
|
||||
reg_info.name = "r9";
|
||||
break;
|
||||
case dwarf_r10:
|
||||
reg_info.name = "r10";
|
||||
break;
|
||||
case dwarf_r11:
|
||||
reg_info.name = "r11";
|
||||
break;
|
||||
case dwarf_r12:
|
||||
reg_info.name = "r12";
|
||||
break;
|
||||
case dwarf_sp:
|
||||
reg_info.name = "sp";
|
||||
reg_info.alt_name = "r13";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
|
||||
break;
|
||||
case dwarf_lr:
|
||||
reg_info.name = "lr";
|
||||
reg_info.alt_name = "r14";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
|
||||
break;
|
||||
case dwarf_pc:
|
||||
reg_info.name = "pc";
|
||||
reg_info.alt_name = "r15";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
|
||||
break;
|
||||
case dwarf_cpsr:
|
||||
reg_info.name = "cpsr";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
|
||||
break;
|
||||
|
||||
case dwarf_s0:
|
||||
reg_info.name = "s0";
|
||||
break;
|
||||
case dwarf_s1:
|
||||
reg_info.name = "s1";
|
||||
break;
|
||||
case dwarf_s2:
|
||||
reg_info.name = "s2";
|
||||
break;
|
||||
case dwarf_s3:
|
||||
reg_info.name = "s3";
|
||||
break;
|
||||
case dwarf_s4:
|
||||
reg_info.name = "s4";
|
||||
break;
|
||||
case dwarf_s5:
|
||||
reg_info.name = "s5";
|
||||
break;
|
||||
case dwarf_s6:
|
||||
reg_info.name = "s6";
|
||||
break;
|
||||
case dwarf_s7:
|
||||
reg_info.name = "s7";
|
||||
break;
|
||||
case dwarf_s8:
|
||||
reg_info.name = "s8";
|
||||
break;
|
||||
case dwarf_s9:
|
||||
reg_info.name = "s9";
|
||||
break;
|
||||
case dwarf_s10:
|
||||
reg_info.name = "s10";
|
||||
break;
|
||||
case dwarf_s11:
|
||||
reg_info.name = "s11";
|
||||
break;
|
||||
case dwarf_s12:
|
||||
reg_info.name = "s12";
|
||||
break;
|
||||
case dwarf_s13:
|
||||
reg_info.name = "s13";
|
||||
break;
|
||||
case dwarf_s14:
|
||||
reg_info.name = "s14";
|
||||
break;
|
||||
case dwarf_s15:
|
||||
reg_info.name = "s15";
|
||||
break;
|
||||
case dwarf_s16:
|
||||
reg_info.name = "s16";
|
||||
break;
|
||||
case dwarf_s17:
|
||||
reg_info.name = "s17";
|
||||
break;
|
||||
case dwarf_s18:
|
||||
reg_info.name = "s18";
|
||||
break;
|
||||
case dwarf_s19:
|
||||
reg_info.name = "s19";
|
||||
break;
|
||||
case dwarf_s20:
|
||||
reg_info.name = "s20";
|
||||
break;
|
||||
case dwarf_s21:
|
||||
reg_info.name = "s21";
|
||||
break;
|
||||
case dwarf_s22:
|
||||
reg_info.name = "s22";
|
||||
break;
|
||||
case dwarf_s23:
|
||||
reg_info.name = "s23";
|
||||
break;
|
||||
case dwarf_s24:
|
||||
reg_info.name = "s24";
|
||||
break;
|
||||
case dwarf_s25:
|
||||
reg_info.name = "s25";
|
||||
break;
|
||||
case dwarf_s26:
|
||||
reg_info.name = "s26";
|
||||
break;
|
||||
case dwarf_s27:
|
||||
reg_info.name = "s27";
|
||||
break;
|
||||
case dwarf_s28:
|
||||
reg_info.name = "s28";
|
||||
break;
|
||||
case dwarf_s29:
|
||||
reg_info.name = "s29";
|
||||
break;
|
||||
case dwarf_s30:
|
||||
reg_info.name = "s30";
|
||||
break;
|
||||
case dwarf_s31:
|
||||
reg_info.name = "s31";
|
||||
break;
|
||||
|
||||
// FPA Registers 0-7
|
||||
case dwarf_f0:
|
||||
reg_info.name = "f0";
|
||||
break;
|
||||
case dwarf_f1:
|
||||
reg_info.name = "f1";
|
||||
break;
|
||||
case dwarf_f2:
|
||||
reg_info.name = "f2";
|
||||
break;
|
||||
case dwarf_f3:
|
||||
reg_info.name = "f3";
|
||||
break;
|
||||
case dwarf_f4:
|
||||
reg_info.name = "f4";
|
||||
break;
|
||||
case dwarf_f5:
|
||||
reg_info.name = "f5";
|
||||
break;
|
||||
case dwarf_f6:
|
||||
reg_info.name = "f6";
|
||||
break;
|
||||
case dwarf_f7:
|
||||
reg_info.name = "f7";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX general purpose registers 0 - 7
|
||||
// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
|
||||
case dwarf_wCGR0:
|
||||
reg_info.name = "wCGR0/ACC0";
|
||||
break;
|
||||
case dwarf_wCGR1:
|
||||
reg_info.name = "wCGR1/ACC1";
|
||||
break;
|
||||
case dwarf_wCGR2:
|
||||
reg_info.name = "wCGR2/ACC2";
|
||||
break;
|
||||
case dwarf_wCGR3:
|
||||
reg_info.name = "wCGR3/ACC3";
|
||||
break;
|
||||
case dwarf_wCGR4:
|
||||
reg_info.name = "wCGR4/ACC4";
|
||||
break;
|
||||
case dwarf_wCGR5:
|
||||
reg_info.name = "wCGR5/ACC5";
|
||||
break;
|
||||
case dwarf_wCGR6:
|
||||
reg_info.name = "wCGR6/ACC6";
|
||||
break;
|
||||
case dwarf_wCGR7:
|
||||
reg_info.name = "wCGR7/ACC7";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX data registers 0 - 15
|
||||
case dwarf_wR0:
|
||||
reg_info.name = "wR0";
|
||||
break;
|
||||
case dwarf_wR1:
|
||||
reg_info.name = "wR1";
|
||||
break;
|
||||
case dwarf_wR2:
|
||||
reg_info.name = "wR2";
|
||||
break;
|
||||
case dwarf_wR3:
|
||||
reg_info.name = "wR3";
|
||||
break;
|
||||
case dwarf_wR4:
|
||||
reg_info.name = "wR4";
|
||||
break;
|
||||
case dwarf_wR5:
|
||||
reg_info.name = "wR5";
|
||||
break;
|
||||
case dwarf_wR6:
|
||||
reg_info.name = "wR6";
|
||||
break;
|
||||
case dwarf_wR7:
|
||||
reg_info.name = "wR7";
|
||||
break;
|
||||
case dwarf_wR8:
|
||||
reg_info.name = "wR8";
|
||||
break;
|
||||
case dwarf_wR9:
|
||||
reg_info.name = "wR9";
|
||||
break;
|
||||
case dwarf_wR10:
|
||||
reg_info.name = "wR10";
|
||||
break;
|
||||
case dwarf_wR11:
|
||||
reg_info.name = "wR11";
|
||||
break;
|
||||
case dwarf_wR12:
|
||||
reg_info.name = "wR12";
|
||||
break;
|
||||
case dwarf_wR13:
|
||||
reg_info.name = "wR13";
|
||||
break;
|
||||
case dwarf_wR14:
|
||||
reg_info.name = "wR14";
|
||||
break;
|
||||
case dwarf_wR15:
|
||||
reg_info.name = "wR15";
|
||||
break;
|
||||
|
||||
case dwarf_spsr:
|
||||
reg_info.name = "spsr";
|
||||
break;
|
||||
case dwarf_spsr_fiq:
|
||||
reg_info.name = "spsr_fiq";
|
||||
break;
|
||||
case dwarf_spsr_irq:
|
||||
reg_info.name = "spsr_irq";
|
||||
break;
|
||||
case dwarf_spsr_abt:
|
||||
reg_info.name = "spsr_abt";
|
||||
break;
|
||||
case dwarf_spsr_und:
|
||||
reg_info.name = "spsr_und";
|
||||
break;
|
||||
case dwarf_spsr_svc:
|
||||
reg_info.name = "spsr_svc";
|
||||
break;
|
||||
|
||||
case dwarf_r8_usr:
|
||||
reg_info.name = "r8_usr";
|
||||
break;
|
||||
case dwarf_r9_usr:
|
||||
reg_info.name = "r9_usr";
|
||||
break;
|
||||
case dwarf_r10_usr:
|
||||
reg_info.name = "r10_usr";
|
||||
break;
|
||||
case dwarf_r11_usr:
|
||||
reg_info.name = "r11_usr";
|
||||
break;
|
||||
case dwarf_r12_usr:
|
||||
reg_info.name = "r12_usr";
|
||||
break;
|
||||
case dwarf_r13_usr:
|
||||
reg_info.name = "r13_usr";
|
||||
break;
|
||||
case dwarf_r14_usr:
|
||||
reg_info.name = "r14_usr";
|
||||
break;
|
||||
case dwarf_r8_fiq:
|
||||
reg_info.name = "r8_fiq";
|
||||
break;
|
||||
case dwarf_r9_fiq:
|
||||
reg_info.name = "r9_fiq";
|
||||
break;
|
||||
case dwarf_r10_fiq:
|
||||
reg_info.name = "r10_fiq";
|
||||
break;
|
||||
case dwarf_r11_fiq:
|
||||
reg_info.name = "r11_fiq";
|
||||
break;
|
||||
case dwarf_r12_fiq:
|
||||
reg_info.name = "r12_fiq";
|
||||
break;
|
||||
case dwarf_r13_fiq:
|
||||
reg_info.name = "r13_fiq";
|
||||
break;
|
||||
case dwarf_r14_fiq:
|
||||
reg_info.name = "r14_fiq";
|
||||
break;
|
||||
case dwarf_r13_irq:
|
||||
reg_info.name = "r13_irq";
|
||||
break;
|
||||
case dwarf_r14_irq:
|
||||
reg_info.name = "r14_irq";
|
||||
break;
|
||||
case dwarf_r13_abt:
|
||||
reg_info.name = "r13_abt";
|
||||
break;
|
||||
case dwarf_r14_abt:
|
||||
reg_info.name = "r14_abt";
|
||||
break;
|
||||
case dwarf_r13_und:
|
||||
reg_info.name = "r13_und";
|
||||
break;
|
||||
case dwarf_r14_und:
|
||||
reg_info.name = "r14_und";
|
||||
break;
|
||||
case dwarf_r13_svc:
|
||||
reg_info.name = "r13_svc";
|
||||
break;
|
||||
case dwarf_r14_svc:
|
||||
reg_info.name = "r14_svc";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX control register in co-processor 0 - 7
|
||||
case dwarf_wC0:
|
||||
reg_info.name = "wC0";
|
||||
break;
|
||||
case dwarf_wC1:
|
||||
reg_info.name = "wC1";
|
||||
break;
|
||||
case dwarf_wC2:
|
||||
reg_info.name = "wC2";
|
||||
break;
|
||||
case dwarf_wC3:
|
||||
reg_info.name = "wC3";
|
||||
break;
|
||||
case dwarf_wC4:
|
||||
reg_info.name = "wC4";
|
||||
break;
|
||||
case dwarf_wC5:
|
||||
reg_info.name = "wC5";
|
||||
break;
|
||||
case dwarf_wC6:
|
||||
reg_info.name = "wC6";
|
||||
break;
|
||||
case dwarf_wC7:
|
||||
reg_info.name = "wC7";
|
||||
break;
|
||||
|
||||
// VFP-v3/Neon
|
||||
case dwarf_d0:
|
||||
reg_info.name = "d0";
|
||||
break;
|
||||
case dwarf_d1:
|
||||
reg_info.name = "d1";
|
||||
break;
|
||||
case dwarf_d2:
|
||||
reg_info.name = "d2";
|
||||
break;
|
||||
case dwarf_d3:
|
||||
reg_info.name = "d3";
|
||||
break;
|
||||
case dwarf_d4:
|
||||
reg_info.name = "d4";
|
||||
break;
|
||||
case dwarf_d5:
|
||||
reg_info.name = "d5";
|
||||
break;
|
||||
case dwarf_d6:
|
||||
reg_info.name = "d6";
|
||||
break;
|
||||
case dwarf_d7:
|
||||
reg_info.name = "d7";
|
||||
break;
|
||||
case dwarf_d8:
|
||||
reg_info.name = "d8";
|
||||
break;
|
||||
case dwarf_d9:
|
||||
reg_info.name = "d9";
|
||||
break;
|
||||
case dwarf_d10:
|
||||
reg_info.name = "d10";
|
||||
break;
|
||||
case dwarf_d11:
|
||||
reg_info.name = "d11";
|
||||
break;
|
||||
case dwarf_d12:
|
||||
reg_info.name = "d12";
|
||||
break;
|
||||
case dwarf_d13:
|
||||
reg_info.name = "d13";
|
||||
break;
|
||||
case dwarf_d14:
|
||||
reg_info.name = "d14";
|
||||
break;
|
||||
case dwarf_d15:
|
||||
reg_info.name = "d15";
|
||||
break;
|
||||
case dwarf_d16:
|
||||
reg_info.name = "d16";
|
||||
break;
|
||||
case dwarf_d17:
|
||||
reg_info.name = "d17";
|
||||
break;
|
||||
case dwarf_d18:
|
||||
reg_info.name = "d18";
|
||||
break;
|
||||
case dwarf_d19:
|
||||
reg_info.name = "d19";
|
||||
break;
|
||||
case dwarf_d20:
|
||||
reg_info.name = "d20";
|
||||
break;
|
||||
case dwarf_d21:
|
||||
reg_info.name = "d21";
|
||||
break;
|
||||
case dwarf_d22:
|
||||
reg_info.name = "d22";
|
||||
break;
|
||||
case dwarf_d23:
|
||||
reg_info.name = "d23";
|
||||
break;
|
||||
case dwarf_d24:
|
||||
reg_info.name = "d24";
|
||||
break;
|
||||
case dwarf_d25:
|
||||
reg_info.name = "d25";
|
||||
break;
|
||||
case dwarf_d26:
|
||||
reg_info.name = "d26";
|
||||
break;
|
||||
case dwarf_d27:
|
||||
reg_info.name = "d27";
|
||||
break;
|
||||
case dwarf_d28:
|
||||
reg_info.name = "d28";
|
||||
break;
|
||||
case dwarf_d29:
|
||||
reg_info.name = "d29";
|
||||
break;
|
||||
case dwarf_d30:
|
||||
reg_info.name = "d30";
|
||||
break;
|
||||
case dwarf_d31:
|
||||
reg_info.name = "d31";
|
||||
break;
|
||||
|
||||
// NEON 128-bit vector registers (overlays the d registers)
|
||||
case dwarf_q0:
|
||||
reg_info.name = "q0";
|
||||
break;
|
||||
case dwarf_q1:
|
||||
reg_info.name = "q1";
|
||||
break;
|
||||
case dwarf_q2:
|
||||
reg_info.name = "q2";
|
||||
break;
|
||||
case dwarf_q3:
|
||||
reg_info.name = "q3";
|
||||
break;
|
||||
case dwarf_q4:
|
||||
reg_info.name = "q4";
|
||||
break;
|
||||
case dwarf_q5:
|
||||
reg_info.name = "q5";
|
||||
break;
|
||||
case dwarf_q6:
|
||||
reg_info.name = "q6";
|
||||
break;
|
||||
case dwarf_q7:
|
||||
reg_info.name = "q7";
|
||||
break;
|
||||
case dwarf_q8:
|
||||
reg_info.name = "q8";
|
||||
break;
|
||||
case dwarf_q9:
|
||||
reg_info.name = "q9";
|
||||
break;
|
||||
case dwarf_q10:
|
||||
reg_info.name = "q10";
|
||||
break;
|
||||
case dwarf_q11:
|
||||
reg_info.name = "q11";
|
||||
break;
|
||||
case dwarf_q12:
|
||||
reg_info.name = "q12";
|
||||
break;
|
||||
case dwarf_q13:
|
||||
reg_info.name = "q13";
|
||||
break;
|
||||
case dwarf_q14:
|
||||
reg_info.name = "q14";
|
||||
break;
|
||||
case dwarf_q15:
|
||||
reg_info.name = "q15";
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// A8.6.50
|
||||
// Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
|
||||
static uint32_t CountITSize(uint32_t ITMask) {
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
#include "lldb/Core/StreamString.h"
|
||||
#include "lldb/Target/ExecutionContext.h"
|
||||
#include "lldb/Target/Target.h"
|
||||
#include "lldb/Utility/Utils.h"
|
||||
// Project includes
|
||||
#include "ProcessGDBRemote.h"
|
||||
#include "ProcessGDBRemoteLog.h"
|
||||
|
|
|
|||
|
|
@ -41,7 +41,6 @@
|
|||
#include "lldb/Target/Process.h"
|
||||
#include "lldb/Target/Target.h"
|
||||
#include "lldb/Target/UnixSignals.h"
|
||||
#include "lldb/Utility/Utils.h"
|
||||
|
||||
// Define these constants from POSIX mman.h rather than include the file
|
||||
// so that they will be correct even when compiled on Linux.
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include "lldb/Target/Thread.h"
|
||||
#include "lldb/Target/ThreadList.h"
|
||||
#include "lldb/Target/ThreadPlan.h"
|
||||
#include "lldb/Utility/ConvertEnum.h"
|
||||
#include "lldb/Utility/LLDBAssert.h"
|
||||
|
||||
using namespace lldb;
|
||||
|
|
@ -384,18 +383,14 @@ Vote ThreadList::ShouldReportStop(Event *event_ptr) {
|
|||
if (result == eVoteNoOpinion) {
|
||||
result = eVoteNo;
|
||||
} else {
|
||||
if (log)
|
||||
log->Printf("ThreadList::%s thread 0x%4.4" PRIx64
|
||||
": voted %s, but lost out because result was %s",
|
||||
__FUNCTION__, thread_sp->GetID(), GetVoteAsCString(vote),
|
||||
GetVoteAsCString(result));
|
||||
LLDB_LOG(log,
|
||||
"Thread {0:x} voted {1}, but lost out because result was {2}",
|
||||
thread_sp->GetID(), vote, result);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (log)
|
||||
log->Printf("ThreadList::%s returning %s", __FUNCTION__,
|
||||
GetVoteAsCString(result));
|
||||
LLDB_LOG(log, "Returning {0}", result);
|
||||
return result;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
#include "lldb/Target/RegisterContext.h"
|
||||
#include "lldb/Target/Target.h"
|
||||
#include "lldb/Target/Thread.h"
|
||||
#include "lldb/Utility/ConvertEnum.h"
|
||||
|
||||
using namespace lldb;
|
||||
using namespace lldb_private;
|
||||
|
|
@ -78,15 +77,13 @@ Vote ThreadPlan::ShouldReportStop(Event *event_ptr) {
|
|||
if (prev_plan) {
|
||||
Vote prev_vote = prev_plan->ShouldReportStop(event_ptr);
|
||||
if (log)
|
||||
log->Printf("ThreadPlan::ShouldReportStop() returning previous thread "
|
||||
"plan vote: %s",
|
||||
GetVoteAsCString(prev_vote));
|
||||
log->Format(__FILE__, __FUNCTION__,
|
||||
"returning previous thread plan vote: {0}", prev_vote);
|
||||
return prev_vote;
|
||||
}
|
||||
}
|
||||
if (log)
|
||||
log->Printf("ThreadPlan::ShouldReportStop() returning vote: %s",
|
||||
GetVoteAsCString(m_stop_vote));
|
||||
log->Printf("Returning vote: {0}", m_stop_vote);
|
||||
return m_stop_vote;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,212 +0,0 @@
|
|||
//===-- ARM64_DWARF_Registers.cpp -------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "ARM64_DWARF_Registers.h"
|
||||
|
||||
using namespace lldb;
|
||||
using namespace lldb_private;
|
||||
using namespace arm64_dwarf;
|
||||
|
||||
const char *arm64_dwarf::GetRegisterName(unsigned reg_num,
|
||||
bool altnernate_name) {
|
||||
if (altnernate_name) {
|
||||
switch (reg_num) {
|
||||
case fp:
|
||||
return "x29";
|
||||
case lr:
|
||||
return "x30";
|
||||
case sp:
|
||||
return "x31";
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
switch (reg_num) {
|
||||
case x0:
|
||||
return "x0";
|
||||
case x1:
|
||||
return "x1";
|
||||
case x2:
|
||||
return "x2";
|
||||
case x3:
|
||||
return "x3";
|
||||
case x4:
|
||||
return "x4";
|
||||
case x5:
|
||||
return "x5";
|
||||
case x6:
|
||||
return "x6";
|
||||
case x7:
|
||||
return "x7";
|
||||
case x8:
|
||||
return "x8";
|
||||
case x9:
|
||||
return "x9";
|
||||
case x10:
|
||||
return "x10";
|
||||
case x11:
|
||||
return "x11";
|
||||
case x12:
|
||||
return "x12";
|
||||
case x13:
|
||||
return "x13";
|
||||
case x14:
|
||||
return "x14";
|
||||
case x15:
|
||||
return "x15";
|
||||
case x16:
|
||||
return "x16";
|
||||
case x17:
|
||||
return "x17";
|
||||
case x18:
|
||||
return "x18";
|
||||
case x19:
|
||||
return "x19";
|
||||
case x20:
|
||||
return "x20";
|
||||
case x21:
|
||||
return "x21";
|
||||
case x22:
|
||||
return "x22";
|
||||
case x23:
|
||||
return "x23";
|
||||
case x24:
|
||||
return "x24";
|
||||
case x25:
|
||||
return "x25";
|
||||
case x26:
|
||||
return "x26";
|
||||
case x27:
|
||||
return "x27";
|
||||
case x28:
|
||||
return "x28";
|
||||
case fp:
|
||||
return "fp";
|
||||
case lr:
|
||||
return "lr";
|
||||
case sp:
|
||||
return "sp";
|
||||
case pc:
|
||||
return "pc";
|
||||
case cpsr:
|
||||
return "cpsr";
|
||||
case v0:
|
||||
return "v0";
|
||||
case v1:
|
||||
return "v1";
|
||||
case v2:
|
||||
return "v2";
|
||||
case v3:
|
||||
return "v3";
|
||||
case v4:
|
||||
return "v4";
|
||||
case v5:
|
||||
return "v5";
|
||||
case v6:
|
||||
return "v6";
|
||||
case v7:
|
||||
return "v7";
|
||||
case v8:
|
||||
return "v8";
|
||||
case v9:
|
||||
return "v9";
|
||||
case v10:
|
||||
return "v10";
|
||||
case v11:
|
||||
return "v11";
|
||||
case v12:
|
||||
return "v12";
|
||||
case v13:
|
||||
return "v13";
|
||||
case v14:
|
||||
return "v14";
|
||||
case v15:
|
||||
return "v15";
|
||||
case v16:
|
||||
return "v16";
|
||||
case v17:
|
||||
return "v17";
|
||||
case v18:
|
||||
return "v18";
|
||||
case v19:
|
||||
return "v19";
|
||||
case v20:
|
||||
return "v20";
|
||||
case v21:
|
||||
return "v21";
|
||||
case v22:
|
||||
return "v22";
|
||||
case v23:
|
||||
return "v23";
|
||||
case v24:
|
||||
return "v24";
|
||||
case v25:
|
||||
return "v25";
|
||||
case v26:
|
||||
return "v26";
|
||||
case v27:
|
||||
return "v27";
|
||||
case v28:
|
||||
return "v28";
|
||||
case v29:
|
||||
return "v29";
|
||||
case v30:
|
||||
return "v30";
|
||||
case v31:
|
||||
return "v31";
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
bool arm64_dwarf::GetRegisterInfo(unsigned reg_num, RegisterInfo ®_info) {
|
||||
::memset(®_info, 0, sizeof(RegisterInfo));
|
||||
::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
|
||||
|
||||
if (reg_num >= x0 && reg_num <= pc) {
|
||||
reg_info.byte_size = 8;
|
||||
reg_info.format = eFormatHex;
|
||||
reg_info.encoding = eEncodingUint;
|
||||
} else if (reg_num >= v0 && reg_num <= v31) {
|
||||
reg_info.byte_size = 16;
|
||||
reg_info.format = eFormatVectorOfFloat32;
|
||||
reg_info.encoding = eEncodingVector;
|
||||
} else if (reg_num == cpsr) {
|
||||
reg_info.byte_size = 4;
|
||||
reg_info.format = eFormatHex;
|
||||
reg_info.encoding = eEncodingUint;
|
||||
} else {
|
||||
return false;
|
||||
}
|
||||
|
||||
reg_info.name = arm64_dwarf::GetRegisterName(reg_num, false);
|
||||
reg_info.alt_name = arm64_dwarf::GetRegisterName(reg_num, true);
|
||||
reg_info.kinds[eRegisterKindDWARF] = reg_num;
|
||||
|
||||
switch (reg_num) {
|
||||
case fp:
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
|
||||
break;
|
||||
case lr:
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
|
||||
break;
|
||||
case sp:
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
|
||||
break;
|
||||
case pc:
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -91,10 +91,6 @@ enum {
|
|||
// 96-127 reserved
|
||||
};
|
||||
|
||||
const char *GetRegisterName(unsigned reg_num, bool altnernate_name);
|
||||
|
||||
bool GetRegisterInfo(unsigned reg_num, lldb_private::RegisterInfo ®_info);
|
||||
|
||||
} // namespace arm64_dwarf
|
||||
|
||||
#endif // utility_ARM64_DWARF_Registers_h_
|
||||
|
|
|
|||
|
|
@ -1,925 +0,0 @@
|
|||
//===-- ARM_DWARF_Registers.cpp ---------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "ARM_DWARF_Registers.h"
|
||||
#include <string.h>
|
||||
|
||||
#include <string.h>
|
||||
|
||||
using namespace lldb;
|
||||
using namespace lldb_private;
|
||||
|
||||
const char *GetARMDWARFRegisterName(unsigned reg_num) {
|
||||
switch (reg_num) {
|
||||
case dwarf_r0:
|
||||
return "r0";
|
||||
case dwarf_r1:
|
||||
return "r1";
|
||||
case dwarf_r2:
|
||||
return "r2";
|
||||
case dwarf_r3:
|
||||
return "r3";
|
||||
case dwarf_r4:
|
||||
return "r4";
|
||||
case dwarf_r5:
|
||||
return "r5";
|
||||
case dwarf_r6:
|
||||
return "r6";
|
||||
case dwarf_r7:
|
||||
return "r7";
|
||||
case dwarf_r8:
|
||||
return "r8";
|
||||
case dwarf_r9:
|
||||
return "r9";
|
||||
case dwarf_r10:
|
||||
return "r10";
|
||||
case dwarf_r11:
|
||||
return "r11";
|
||||
case dwarf_r12:
|
||||
return "r12";
|
||||
case dwarf_sp:
|
||||
return "sp";
|
||||
case dwarf_lr:
|
||||
return "lr";
|
||||
case dwarf_pc:
|
||||
return "pc";
|
||||
case dwarf_cpsr:
|
||||
return "cpsr";
|
||||
|
||||
case dwarf_s0:
|
||||
return "s0";
|
||||
case dwarf_s1:
|
||||
return "s1";
|
||||
case dwarf_s2:
|
||||
return "s2";
|
||||
case dwarf_s3:
|
||||
return "s3";
|
||||
case dwarf_s4:
|
||||
return "s4";
|
||||
case dwarf_s5:
|
||||
return "s5";
|
||||
case dwarf_s6:
|
||||
return "s6";
|
||||
case dwarf_s7:
|
||||
return "s7";
|
||||
case dwarf_s8:
|
||||
return "s8";
|
||||
case dwarf_s9:
|
||||
return "s9";
|
||||
case dwarf_s10:
|
||||
return "s10";
|
||||
case dwarf_s11:
|
||||
return "s11";
|
||||
case dwarf_s12:
|
||||
return "s12";
|
||||
case dwarf_s13:
|
||||
return "s13";
|
||||
case dwarf_s14:
|
||||
return "s14";
|
||||
case dwarf_s15:
|
||||
return "s15";
|
||||
case dwarf_s16:
|
||||
return "s16";
|
||||
case dwarf_s17:
|
||||
return "s17";
|
||||
case dwarf_s18:
|
||||
return "s18";
|
||||
case dwarf_s19:
|
||||
return "s19";
|
||||
case dwarf_s20:
|
||||
return "s20";
|
||||
case dwarf_s21:
|
||||
return "s21";
|
||||
case dwarf_s22:
|
||||
return "s22";
|
||||
case dwarf_s23:
|
||||
return "s23";
|
||||
case dwarf_s24:
|
||||
return "s24";
|
||||
case dwarf_s25:
|
||||
return "s25";
|
||||
case dwarf_s26:
|
||||
return "s26";
|
||||
case dwarf_s27:
|
||||
return "s27";
|
||||
case dwarf_s28:
|
||||
return "s28";
|
||||
case dwarf_s29:
|
||||
return "s29";
|
||||
case dwarf_s30:
|
||||
return "s30";
|
||||
case dwarf_s31:
|
||||
return "s31";
|
||||
|
||||
// FPA Registers 0-7
|
||||
case dwarf_f0:
|
||||
return "f0";
|
||||
case dwarf_f1:
|
||||
return "f1";
|
||||
case dwarf_f2:
|
||||
return "f2";
|
||||
case dwarf_f3:
|
||||
return "f3";
|
||||
case dwarf_f4:
|
||||
return "f4";
|
||||
case dwarf_f5:
|
||||
return "f5";
|
||||
case dwarf_f6:
|
||||
return "f6";
|
||||
case dwarf_f7:
|
||||
return "f7";
|
||||
|
||||
// Intel wireless MMX general purpose registers 0 - 7
|
||||
// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
|
||||
case dwarf_wCGR0:
|
||||
return "wCGR0/ACC0";
|
||||
case dwarf_wCGR1:
|
||||
return "wCGR1/ACC1";
|
||||
case dwarf_wCGR2:
|
||||
return "wCGR2/ACC2";
|
||||
case dwarf_wCGR3:
|
||||
return "wCGR3/ACC3";
|
||||
case dwarf_wCGR4:
|
||||
return "wCGR4/ACC4";
|
||||
case dwarf_wCGR5:
|
||||
return "wCGR5/ACC5";
|
||||
case dwarf_wCGR6:
|
||||
return "wCGR6/ACC6";
|
||||
case dwarf_wCGR7:
|
||||
return "wCGR7/ACC7";
|
||||
|
||||
// Intel wireless MMX data registers 0 - 15
|
||||
case dwarf_wR0:
|
||||
return "wR0";
|
||||
case dwarf_wR1:
|
||||
return "wR1";
|
||||
case dwarf_wR2:
|
||||
return "wR2";
|
||||
case dwarf_wR3:
|
||||
return "wR3";
|
||||
case dwarf_wR4:
|
||||
return "wR4";
|
||||
case dwarf_wR5:
|
||||
return "wR5";
|
||||
case dwarf_wR6:
|
||||
return "wR6";
|
||||
case dwarf_wR7:
|
||||
return "wR7";
|
||||
case dwarf_wR8:
|
||||
return "wR8";
|
||||
case dwarf_wR9:
|
||||
return "wR9";
|
||||
case dwarf_wR10:
|
||||
return "wR10";
|
||||
case dwarf_wR11:
|
||||
return "wR11";
|
||||
case dwarf_wR12:
|
||||
return "wR12";
|
||||
case dwarf_wR13:
|
||||
return "wR13";
|
||||
case dwarf_wR14:
|
||||
return "wR14";
|
||||
case dwarf_wR15:
|
||||
return "wR15";
|
||||
|
||||
case dwarf_spsr:
|
||||
return "spsr";
|
||||
case dwarf_spsr_fiq:
|
||||
return "spsr_fiq";
|
||||
case dwarf_spsr_irq:
|
||||
return "spsr_irq";
|
||||
case dwarf_spsr_abt:
|
||||
return "spsr_abt";
|
||||
case dwarf_spsr_und:
|
||||
return "spsr_und";
|
||||
case dwarf_spsr_svc:
|
||||
return "spsr_svc";
|
||||
|
||||
case dwarf_r8_usr:
|
||||
return "r8_usr";
|
||||
case dwarf_r9_usr:
|
||||
return "r9_usr";
|
||||
case dwarf_r10_usr:
|
||||
return "r10_usr";
|
||||
case dwarf_r11_usr:
|
||||
return "r11_usr";
|
||||
case dwarf_r12_usr:
|
||||
return "r12_usr";
|
||||
case dwarf_r13_usr:
|
||||
return "r13_usr";
|
||||
case dwarf_r14_usr:
|
||||
return "r14_usr";
|
||||
case dwarf_r8_fiq:
|
||||
return "r8_fiq";
|
||||
case dwarf_r9_fiq:
|
||||
return "r9_fiq";
|
||||
case dwarf_r10_fiq:
|
||||
return "r10_fiq";
|
||||
case dwarf_r11_fiq:
|
||||
return "r11_fiq";
|
||||
case dwarf_r12_fiq:
|
||||
return "r12_fiq";
|
||||
case dwarf_r13_fiq:
|
||||
return "r13_fiq";
|
||||
case dwarf_r14_fiq:
|
||||
return "r14_fiq";
|
||||
case dwarf_r13_irq:
|
||||
return "r13_irq";
|
||||
case dwarf_r14_irq:
|
||||
return "r14_irq";
|
||||
case dwarf_r13_abt:
|
||||
return "r13_abt";
|
||||
case dwarf_r14_abt:
|
||||
return "r14_abt";
|
||||
case dwarf_r13_und:
|
||||
return "r13_und";
|
||||
case dwarf_r14_und:
|
||||
return "r14_und";
|
||||
case dwarf_r13_svc:
|
||||
return "r13_svc";
|
||||
case dwarf_r14_svc:
|
||||
return "r14_svc";
|
||||
|
||||
// Intel wireless MMX control register in co-processor 0 - 7
|
||||
case dwarf_wC0:
|
||||
return "wC0";
|
||||
case dwarf_wC1:
|
||||
return "wC1";
|
||||
case dwarf_wC2:
|
||||
return "wC2";
|
||||
case dwarf_wC3:
|
||||
return "wC3";
|
||||
case dwarf_wC4:
|
||||
return "wC4";
|
||||
case dwarf_wC5:
|
||||
return "wC5";
|
||||
case dwarf_wC6:
|
||||
return "wC6";
|
||||
case dwarf_wC7:
|
||||
return "wC7";
|
||||
|
||||
// VFP-v3/Neon
|
||||
case dwarf_d0:
|
||||
return "d0";
|
||||
case dwarf_d1:
|
||||
return "d1";
|
||||
case dwarf_d2:
|
||||
return "d2";
|
||||
case dwarf_d3:
|
||||
return "d3";
|
||||
case dwarf_d4:
|
||||
return "d4";
|
||||
case dwarf_d5:
|
||||
return "d5";
|
||||
case dwarf_d6:
|
||||
return "d6";
|
||||
case dwarf_d7:
|
||||
return "d7";
|
||||
case dwarf_d8:
|
||||
return "d8";
|
||||
case dwarf_d9:
|
||||
return "d9";
|
||||
case dwarf_d10:
|
||||
return "d10";
|
||||
case dwarf_d11:
|
||||
return "d11";
|
||||
case dwarf_d12:
|
||||
return "d12";
|
||||
case dwarf_d13:
|
||||
return "d13";
|
||||
case dwarf_d14:
|
||||
return "d14";
|
||||
case dwarf_d15:
|
||||
return "d15";
|
||||
case dwarf_d16:
|
||||
return "d16";
|
||||
case dwarf_d17:
|
||||
return "d17";
|
||||
case dwarf_d18:
|
||||
return "d18";
|
||||
case dwarf_d19:
|
||||
return "d19";
|
||||
case dwarf_d20:
|
||||
return "d20";
|
||||
case dwarf_d21:
|
||||
return "d21";
|
||||
case dwarf_d22:
|
||||
return "d22";
|
||||
case dwarf_d23:
|
||||
return "d23";
|
||||
case dwarf_d24:
|
||||
return "d24";
|
||||
case dwarf_d25:
|
||||
return "d25";
|
||||
case dwarf_d26:
|
||||
return "d26";
|
||||
case dwarf_d27:
|
||||
return "d27";
|
||||
case dwarf_d28:
|
||||
return "d28";
|
||||
case dwarf_d29:
|
||||
return "d29";
|
||||
case dwarf_d30:
|
||||
return "d30";
|
||||
case dwarf_d31:
|
||||
return "d31";
|
||||
|
||||
// NEON 128-bit vector registers (overlays the d registers)
|
||||
case dwarf_q0:
|
||||
return "q0";
|
||||
case dwarf_q1:
|
||||
return "q1";
|
||||
case dwarf_q2:
|
||||
return "q2";
|
||||
case dwarf_q3:
|
||||
return "q3";
|
||||
case dwarf_q4:
|
||||
return "q4";
|
||||
case dwarf_q5:
|
||||
return "q5";
|
||||
case dwarf_q6:
|
||||
return "q6";
|
||||
case dwarf_q7:
|
||||
return "q7";
|
||||
case dwarf_q8:
|
||||
return "q8";
|
||||
case dwarf_q9:
|
||||
return "q9";
|
||||
case dwarf_q10:
|
||||
return "q10";
|
||||
case dwarf_q11:
|
||||
return "q11";
|
||||
case dwarf_q12:
|
||||
return "q12";
|
||||
case dwarf_q13:
|
||||
return "q13";
|
||||
case dwarf_q14:
|
||||
return "q14";
|
||||
case dwarf_q15:
|
||||
return "q15";
|
||||
}
|
||||
return nullptr;
|
||||
}
|
||||
|
||||
bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo ®_info) {
|
||||
::memset(®_info, 0, sizeof(RegisterInfo));
|
||||
::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
|
||||
|
||||
if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
|
||||
reg_info.byte_size = 16;
|
||||
reg_info.format = eFormatVectorOfUInt8;
|
||||
reg_info.encoding = eEncodingVector;
|
||||
}
|
||||
|
||||
if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
|
||||
reg_info.byte_size = 8;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
|
||||
reg_info.byte_size = 4;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
|
||||
reg_info.byte_size = 12;
|
||||
reg_info.format = eFormatFloat;
|
||||
reg_info.encoding = eEncodingIEEE754;
|
||||
} else {
|
||||
reg_info.byte_size = 4;
|
||||
reg_info.format = eFormatHex;
|
||||
reg_info.encoding = eEncodingUint;
|
||||
}
|
||||
|
||||
reg_info.kinds[eRegisterKindDWARF] = reg_num;
|
||||
|
||||
switch (reg_num) {
|
||||
case dwarf_r0:
|
||||
reg_info.name = "r0";
|
||||
break;
|
||||
case dwarf_r1:
|
||||
reg_info.name = "r1";
|
||||
break;
|
||||
case dwarf_r2:
|
||||
reg_info.name = "r2";
|
||||
break;
|
||||
case dwarf_r3:
|
||||
reg_info.name = "r3";
|
||||
break;
|
||||
case dwarf_r4:
|
||||
reg_info.name = "r4";
|
||||
break;
|
||||
case dwarf_r5:
|
||||
reg_info.name = "r5";
|
||||
break;
|
||||
case dwarf_r6:
|
||||
reg_info.name = "r6";
|
||||
break;
|
||||
case dwarf_r7:
|
||||
reg_info.name = "r7";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
|
||||
break;
|
||||
case dwarf_r8:
|
||||
reg_info.name = "r8";
|
||||
break;
|
||||
case dwarf_r9:
|
||||
reg_info.name = "r9";
|
||||
break;
|
||||
case dwarf_r10:
|
||||
reg_info.name = "r10";
|
||||
break;
|
||||
case dwarf_r11:
|
||||
reg_info.name = "r11";
|
||||
break;
|
||||
case dwarf_r12:
|
||||
reg_info.name = "r12";
|
||||
break;
|
||||
case dwarf_sp:
|
||||
reg_info.name = "sp";
|
||||
reg_info.alt_name = "r13";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
|
||||
break;
|
||||
case dwarf_lr:
|
||||
reg_info.name = "lr";
|
||||
reg_info.alt_name = "r14";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
|
||||
break;
|
||||
case dwarf_pc:
|
||||
reg_info.name = "pc";
|
||||
reg_info.alt_name = "r15";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
|
||||
break;
|
||||
case dwarf_cpsr:
|
||||
reg_info.name = "cpsr";
|
||||
reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
|
||||
break;
|
||||
|
||||
case dwarf_s0:
|
||||
reg_info.name = "s0";
|
||||
break;
|
||||
case dwarf_s1:
|
||||
reg_info.name = "s1";
|
||||
break;
|
||||
case dwarf_s2:
|
||||
reg_info.name = "s2";
|
||||
break;
|
||||
case dwarf_s3:
|
||||
reg_info.name = "s3";
|
||||
break;
|
||||
case dwarf_s4:
|
||||
reg_info.name = "s4";
|
||||
break;
|
||||
case dwarf_s5:
|
||||
reg_info.name = "s5";
|
||||
break;
|
||||
case dwarf_s6:
|
||||
reg_info.name = "s6";
|
||||
break;
|
||||
case dwarf_s7:
|
||||
reg_info.name = "s7";
|
||||
break;
|
||||
case dwarf_s8:
|
||||
reg_info.name = "s8";
|
||||
break;
|
||||
case dwarf_s9:
|
||||
reg_info.name = "s9";
|
||||
break;
|
||||
case dwarf_s10:
|
||||
reg_info.name = "s10";
|
||||
break;
|
||||
case dwarf_s11:
|
||||
reg_info.name = "s11";
|
||||
break;
|
||||
case dwarf_s12:
|
||||
reg_info.name = "s12";
|
||||
break;
|
||||
case dwarf_s13:
|
||||
reg_info.name = "s13";
|
||||
break;
|
||||
case dwarf_s14:
|
||||
reg_info.name = "s14";
|
||||
break;
|
||||
case dwarf_s15:
|
||||
reg_info.name = "s15";
|
||||
break;
|
||||
case dwarf_s16:
|
||||
reg_info.name = "s16";
|
||||
break;
|
||||
case dwarf_s17:
|
||||
reg_info.name = "s17";
|
||||
break;
|
||||
case dwarf_s18:
|
||||
reg_info.name = "s18";
|
||||
break;
|
||||
case dwarf_s19:
|
||||
reg_info.name = "s19";
|
||||
break;
|
||||
case dwarf_s20:
|
||||
reg_info.name = "s20";
|
||||
break;
|
||||
case dwarf_s21:
|
||||
reg_info.name = "s21";
|
||||
break;
|
||||
case dwarf_s22:
|
||||
reg_info.name = "s22";
|
||||
break;
|
||||
case dwarf_s23:
|
||||
reg_info.name = "s23";
|
||||
break;
|
||||
case dwarf_s24:
|
||||
reg_info.name = "s24";
|
||||
break;
|
||||
case dwarf_s25:
|
||||
reg_info.name = "s25";
|
||||
break;
|
||||
case dwarf_s26:
|
||||
reg_info.name = "s26";
|
||||
break;
|
||||
case dwarf_s27:
|
||||
reg_info.name = "s27";
|
||||
break;
|
||||
case dwarf_s28:
|
||||
reg_info.name = "s28";
|
||||
break;
|
||||
case dwarf_s29:
|
||||
reg_info.name = "s29";
|
||||
break;
|
||||
case dwarf_s30:
|
||||
reg_info.name = "s30";
|
||||
break;
|
||||
case dwarf_s31:
|
||||
reg_info.name = "s31";
|
||||
break;
|
||||
|
||||
// FPA Registers 0-7
|
||||
case dwarf_f0:
|
||||
reg_info.name = "f0";
|
||||
break;
|
||||
case dwarf_f1:
|
||||
reg_info.name = "f1";
|
||||
break;
|
||||
case dwarf_f2:
|
||||
reg_info.name = "f2";
|
||||
break;
|
||||
case dwarf_f3:
|
||||
reg_info.name = "f3";
|
||||
break;
|
||||
case dwarf_f4:
|
||||
reg_info.name = "f4";
|
||||
break;
|
||||
case dwarf_f5:
|
||||
reg_info.name = "f5";
|
||||
break;
|
||||
case dwarf_f6:
|
||||
reg_info.name = "f6";
|
||||
break;
|
||||
case dwarf_f7:
|
||||
reg_info.name = "f7";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX general purpose registers 0 - 7
|
||||
// XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
|
||||
case dwarf_wCGR0:
|
||||
reg_info.name = "wCGR0/ACC0";
|
||||
break;
|
||||
case dwarf_wCGR1:
|
||||
reg_info.name = "wCGR1/ACC1";
|
||||
break;
|
||||
case dwarf_wCGR2:
|
||||
reg_info.name = "wCGR2/ACC2";
|
||||
break;
|
||||
case dwarf_wCGR3:
|
||||
reg_info.name = "wCGR3/ACC3";
|
||||
break;
|
||||
case dwarf_wCGR4:
|
||||
reg_info.name = "wCGR4/ACC4";
|
||||
break;
|
||||
case dwarf_wCGR5:
|
||||
reg_info.name = "wCGR5/ACC5";
|
||||
break;
|
||||
case dwarf_wCGR6:
|
||||
reg_info.name = "wCGR6/ACC6";
|
||||
break;
|
||||
case dwarf_wCGR7:
|
||||
reg_info.name = "wCGR7/ACC7";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX data registers 0 - 15
|
||||
case dwarf_wR0:
|
||||
reg_info.name = "wR0";
|
||||
break;
|
||||
case dwarf_wR1:
|
||||
reg_info.name = "wR1";
|
||||
break;
|
||||
case dwarf_wR2:
|
||||
reg_info.name = "wR2";
|
||||
break;
|
||||
case dwarf_wR3:
|
||||
reg_info.name = "wR3";
|
||||
break;
|
||||
case dwarf_wR4:
|
||||
reg_info.name = "wR4";
|
||||
break;
|
||||
case dwarf_wR5:
|
||||
reg_info.name = "wR5";
|
||||
break;
|
||||
case dwarf_wR6:
|
||||
reg_info.name = "wR6";
|
||||
break;
|
||||
case dwarf_wR7:
|
||||
reg_info.name = "wR7";
|
||||
break;
|
||||
case dwarf_wR8:
|
||||
reg_info.name = "wR8";
|
||||
break;
|
||||
case dwarf_wR9:
|
||||
reg_info.name = "wR9";
|
||||
break;
|
||||
case dwarf_wR10:
|
||||
reg_info.name = "wR10";
|
||||
break;
|
||||
case dwarf_wR11:
|
||||
reg_info.name = "wR11";
|
||||
break;
|
||||
case dwarf_wR12:
|
||||
reg_info.name = "wR12";
|
||||
break;
|
||||
case dwarf_wR13:
|
||||
reg_info.name = "wR13";
|
||||
break;
|
||||
case dwarf_wR14:
|
||||
reg_info.name = "wR14";
|
||||
break;
|
||||
case dwarf_wR15:
|
||||
reg_info.name = "wR15";
|
||||
break;
|
||||
|
||||
case dwarf_spsr:
|
||||
reg_info.name = "spsr";
|
||||
break;
|
||||
case dwarf_spsr_fiq:
|
||||
reg_info.name = "spsr_fiq";
|
||||
break;
|
||||
case dwarf_spsr_irq:
|
||||
reg_info.name = "spsr_irq";
|
||||
break;
|
||||
case dwarf_spsr_abt:
|
||||
reg_info.name = "spsr_abt";
|
||||
break;
|
||||
case dwarf_spsr_und:
|
||||
reg_info.name = "spsr_und";
|
||||
break;
|
||||
case dwarf_spsr_svc:
|
||||
reg_info.name = "spsr_svc";
|
||||
break;
|
||||
|
||||
case dwarf_r8_usr:
|
||||
reg_info.name = "r8_usr";
|
||||
break;
|
||||
case dwarf_r9_usr:
|
||||
reg_info.name = "r9_usr";
|
||||
break;
|
||||
case dwarf_r10_usr:
|
||||
reg_info.name = "r10_usr";
|
||||
break;
|
||||
case dwarf_r11_usr:
|
||||
reg_info.name = "r11_usr";
|
||||
break;
|
||||
case dwarf_r12_usr:
|
||||
reg_info.name = "r12_usr";
|
||||
break;
|
||||
case dwarf_r13_usr:
|
||||
reg_info.name = "r13_usr";
|
||||
break;
|
||||
case dwarf_r14_usr:
|
||||
reg_info.name = "r14_usr";
|
||||
break;
|
||||
case dwarf_r8_fiq:
|
||||
reg_info.name = "r8_fiq";
|
||||
break;
|
||||
case dwarf_r9_fiq:
|
||||
reg_info.name = "r9_fiq";
|
||||
break;
|
||||
case dwarf_r10_fiq:
|
||||
reg_info.name = "r10_fiq";
|
||||
break;
|
||||
case dwarf_r11_fiq:
|
||||
reg_info.name = "r11_fiq";
|
||||
break;
|
||||
case dwarf_r12_fiq:
|
||||
reg_info.name = "r12_fiq";
|
||||
break;
|
||||
case dwarf_r13_fiq:
|
||||
reg_info.name = "r13_fiq";
|
||||
break;
|
||||
case dwarf_r14_fiq:
|
||||
reg_info.name = "r14_fiq";
|
||||
break;
|
||||
case dwarf_r13_irq:
|
||||
reg_info.name = "r13_irq";
|
||||
break;
|
||||
case dwarf_r14_irq:
|
||||
reg_info.name = "r14_irq";
|
||||
break;
|
||||
case dwarf_r13_abt:
|
||||
reg_info.name = "r13_abt";
|
||||
break;
|
||||
case dwarf_r14_abt:
|
||||
reg_info.name = "r14_abt";
|
||||
break;
|
||||
case dwarf_r13_und:
|
||||
reg_info.name = "r13_und";
|
||||
break;
|
||||
case dwarf_r14_und:
|
||||
reg_info.name = "r14_und";
|
||||
break;
|
||||
case dwarf_r13_svc:
|
||||
reg_info.name = "r13_svc";
|
||||
break;
|
||||
case dwarf_r14_svc:
|
||||
reg_info.name = "r14_svc";
|
||||
break;
|
||||
|
||||
// Intel wireless MMX control register in co-processor 0 - 7
|
||||
case dwarf_wC0:
|
||||
reg_info.name = "wC0";
|
||||
break;
|
||||
case dwarf_wC1:
|
||||
reg_info.name = "wC1";
|
||||
break;
|
||||
case dwarf_wC2:
|
||||
reg_info.name = "wC2";
|
||||
break;
|
||||
case dwarf_wC3:
|
||||
reg_info.name = "wC3";
|
||||
break;
|
||||
case dwarf_wC4:
|
||||
reg_info.name = "wC4";
|
||||
break;
|
||||
case dwarf_wC5:
|
||||
reg_info.name = "wC5";
|
||||
break;
|
||||
case dwarf_wC6:
|
||||
reg_info.name = "wC6";
|
||||
break;
|
||||
case dwarf_wC7:
|
||||
reg_info.name = "wC7";
|
||||
break;
|
||||
|
||||
// VFP-v3/Neon
|
||||
case dwarf_d0:
|
||||
reg_info.name = "d0";
|
||||
break;
|
||||
case dwarf_d1:
|
||||
reg_info.name = "d1";
|
||||
break;
|
||||
case dwarf_d2:
|
||||
reg_info.name = "d2";
|
||||
break;
|
||||
case dwarf_d3:
|
||||
reg_info.name = "d3";
|
||||
break;
|
||||
case dwarf_d4:
|
||||
reg_info.name = "d4";
|
||||
break;
|
||||
case dwarf_d5:
|
||||
reg_info.name = "d5";
|
||||
break;
|
||||
case dwarf_d6:
|
||||
reg_info.name = "d6";
|
||||
break;
|
||||
case dwarf_d7:
|
||||
reg_info.name = "d7";
|
||||
break;
|
||||
case dwarf_d8:
|
||||
reg_info.name = "d8";
|
||||
break;
|
||||
case dwarf_d9:
|
||||
reg_info.name = "d9";
|
||||
break;
|
||||
case dwarf_d10:
|
||||
reg_info.name = "d10";
|
||||
break;
|
||||
case dwarf_d11:
|
||||
reg_info.name = "d11";
|
||||
break;
|
||||
case dwarf_d12:
|
||||
reg_info.name = "d12";
|
||||
break;
|
||||
case dwarf_d13:
|
||||
reg_info.name = "d13";
|
||||
break;
|
||||
case dwarf_d14:
|
||||
reg_info.name = "d14";
|
||||
break;
|
||||
case dwarf_d15:
|
||||
reg_info.name = "d15";
|
||||
break;
|
||||
case dwarf_d16:
|
||||
reg_info.name = "d16";
|
||||
break;
|
||||
case dwarf_d17:
|
||||
reg_info.name = "d17";
|
||||
break;
|
||||
case dwarf_d18:
|
||||
reg_info.name = "d18";
|
||||
break;
|
||||
case dwarf_d19:
|
||||
reg_info.name = "d19";
|
||||
break;
|
||||
case dwarf_d20:
|
||||
reg_info.name = "d20";
|
||||
break;
|
||||
case dwarf_d21:
|
||||
reg_info.name = "d21";
|
||||
break;
|
||||
case dwarf_d22:
|
||||
reg_info.name = "d22";
|
||||
break;
|
||||
case dwarf_d23:
|
||||
reg_info.name = "d23";
|
||||
break;
|
||||
case dwarf_d24:
|
||||
reg_info.name = "d24";
|
||||
break;
|
||||
case dwarf_d25:
|
||||
reg_info.name = "d25";
|
||||
break;
|
||||
case dwarf_d26:
|
||||
reg_info.name = "d26";
|
||||
break;
|
||||
case dwarf_d27:
|
||||
reg_info.name = "d27";
|
||||
break;
|
||||
case dwarf_d28:
|
||||
reg_info.name = "d28";
|
||||
break;
|
||||
case dwarf_d29:
|
||||
reg_info.name = "d29";
|
||||
break;
|
||||
case dwarf_d30:
|
||||
reg_info.name = "d30";
|
||||
break;
|
||||
case dwarf_d31:
|
||||
reg_info.name = "d31";
|
||||
break;
|
||||
|
||||
// NEON 128-bit vector registers (overlays the d registers)
|
||||
case dwarf_q0:
|
||||
reg_info.name = "q0";
|
||||
break;
|
||||
case dwarf_q1:
|
||||
reg_info.name = "q1";
|
||||
break;
|
||||
case dwarf_q2:
|
||||
reg_info.name = "q2";
|
||||
break;
|
||||
case dwarf_q3:
|
||||
reg_info.name = "q3";
|
||||
break;
|
||||
case dwarf_q4:
|
||||
reg_info.name = "q4";
|
||||
break;
|
||||
case dwarf_q5:
|
||||
reg_info.name = "q5";
|
||||
break;
|
||||
case dwarf_q6:
|
||||
reg_info.name = "q6";
|
||||
break;
|
||||
case dwarf_q7:
|
||||
reg_info.name = "q7";
|
||||
break;
|
||||
case dwarf_q8:
|
||||
reg_info.name = "q8";
|
||||
break;
|
||||
case dwarf_q9:
|
||||
reg_info.name = "q9";
|
||||
break;
|
||||
case dwarf_q10:
|
||||
reg_info.name = "q10";
|
||||
break;
|
||||
case dwarf_q11:
|
||||
reg_info.name = "q11";
|
||||
break;
|
||||
case dwarf_q12:
|
||||
reg_info.name = "q12";
|
||||
break;
|
||||
case dwarf_q13:
|
||||
reg_info.name = "q13";
|
||||
break;
|
||||
case dwarf_q14:
|
||||
reg_info.name = "q14";
|
||||
break;
|
||||
case dwarf_q15:
|
||||
reg_info.name = "q15";
|
||||
break;
|
||||
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
@ -205,9 +205,4 @@ enum {
|
|||
dwarf_q15
|
||||
};
|
||||
|
||||
const char *GetARMDWARFRegisterName(unsigned reg_num);
|
||||
|
||||
bool GetARMDWARFRegisterInfo(unsigned reg_num,
|
||||
lldb_private::RegisterInfo ®_info);
|
||||
|
||||
#endif // utility_ARM_DWARF_Registers_h_
|
||||
|
|
|
|||
|
|
@ -1,7 +1,4 @@
|
|||
add_lldb_library(lldbUtility
|
||||
ARM_DWARF_Registers.cpp
|
||||
ARM64_DWARF_Registers.cpp
|
||||
ConvertEnum.cpp
|
||||
JSON.cpp
|
||||
LLDBAssert.cpp
|
||||
ModuleCache.cpp
|
||||
|
|
|
|||
|
|
@ -1,118 +0,0 @@
|
|||
//===-- ConvertEnum.cpp -----------------------------------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
#include "lldb/Utility/ConvertEnum.h"
|
||||
|
||||
using namespace lldb;
|
||||
using namespace lldb_private;
|
||||
|
||||
const char *lldb_private::GetVoteAsCString(Vote vote) {
|
||||
switch (vote) {
|
||||
case eVoteNo:
|
||||
return "no";
|
||||
case eVoteNoOpinion:
|
||||
return "no opinion";
|
||||
case eVoteYes:
|
||||
return "yes";
|
||||
}
|
||||
return "invalid";
|
||||
}
|
||||
|
||||
const char *lldb_private::GetSectionTypeAsCString(lldb::SectionType sect_type) {
|
||||
switch (sect_type) {
|
||||
case eSectionTypeInvalid:
|
||||
return "invalid";
|
||||
case eSectionTypeCode:
|
||||
return "code";
|
||||
case eSectionTypeContainer:
|
||||
return "container";
|
||||
case eSectionTypeData:
|
||||
return "data";
|
||||
case eSectionTypeDataCString:
|
||||
return "data-cstr";
|
||||
case eSectionTypeDataCStringPointers:
|
||||
return "data-cstr-ptr";
|
||||
case eSectionTypeDataSymbolAddress:
|
||||
return "data-symbol-addr";
|
||||
case eSectionTypeData4:
|
||||
return "data-4-byte";
|
||||
case eSectionTypeData8:
|
||||
return "data-8-byte";
|
||||
case eSectionTypeData16:
|
||||
return "data-16-byte";
|
||||
case eSectionTypeDataPointers:
|
||||
return "data-ptrs";
|
||||
case eSectionTypeDebug:
|
||||
return "debug";
|
||||
case eSectionTypeZeroFill:
|
||||
return "zero-fill";
|
||||
case eSectionTypeDataObjCMessageRefs:
|
||||
return "objc-message-refs";
|
||||
case eSectionTypeDataObjCCFStrings:
|
||||
return "objc-cfstrings";
|
||||
case eSectionTypeDWARFDebugAbbrev:
|
||||
return "dwarf-abbrev";
|
||||
case eSectionTypeDWARFDebugAddr:
|
||||
return "dwarf-addr";
|
||||
case eSectionTypeDWARFDebugAranges:
|
||||
return "dwarf-aranges";
|
||||
case eSectionTypeDWARFDebugFrame:
|
||||
return "dwarf-frame";
|
||||
case eSectionTypeDWARFDebugInfo:
|
||||
return "dwarf-info";
|
||||
case eSectionTypeDWARFDebugLine:
|
||||
return "dwarf-line";
|
||||
case eSectionTypeDWARFDebugLoc:
|
||||
return "dwarf-loc";
|
||||
case eSectionTypeDWARFDebugMacInfo:
|
||||
return "dwarf-macinfo";
|
||||
case eSectionTypeDWARFDebugMacro:
|
||||
return "dwarf-macro";
|
||||
case eSectionTypeDWARFDebugPubNames:
|
||||
return "dwarf-pubnames";
|
||||
case eSectionTypeDWARFDebugPubTypes:
|
||||
return "dwarf-pubtypes";
|
||||
case eSectionTypeDWARFDebugRanges:
|
||||
return "dwarf-ranges";
|
||||
case eSectionTypeDWARFDebugStr:
|
||||
return "dwarf-str";
|
||||
case eSectionTypeDWARFDebugStrOffsets:
|
||||
return "dwarf-str-offsets";
|
||||
case eSectionTypeELFSymbolTable:
|
||||
return "elf-symbol-table";
|
||||
case eSectionTypeELFDynamicSymbols:
|
||||
return "elf-dynamic-symbols";
|
||||
case eSectionTypeELFRelocationEntries:
|
||||
return "elf-relocation-entries";
|
||||
case eSectionTypeELFDynamicLinkInfo:
|
||||
return "elf-dynamic-link-info";
|
||||
case eSectionTypeDWARFAppleNames:
|
||||
return "apple-names";
|
||||
case eSectionTypeDWARFAppleTypes:
|
||||
return "apple-types";
|
||||
case eSectionTypeDWARFAppleNamespaces:
|
||||
return "apple-namespaces";
|
||||
case eSectionTypeDWARFAppleObjC:
|
||||
return "apple-objc";
|
||||
case eSectionTypeEHFrame:
|
||||
return "eh-frame";
|
||||
case eSectionTypeARMexidx:
|
||||
return "ARM.exidx";
|
||||
case eSectionTypeARMextab:
|
||||
return "ARM.extab";
|
||||
case eSectionTypeCompactUnwind:
|
||||
return "compact-unwind";
|
||||
case eSectionTypeGoSymtab:
|
||||
return "go-symtab";
|
||||
case eSectionTypeAbsoluteAddress:
|
||||
return "absolute";
|
||||
case eSectionTypeOther:
|
||||
return "regular";
|
||||
}
|
||||
return "unknown";
|
||||
}
|
||||
Loading…
Reference in New Issue