forked from OSchip/llvm-project
AMDGPU: Select i8/i16 global and flat atomic load/store
As far as I know these should be atomic anyway, as long as the address is aligned. Unaligned atomics hit an ugly error in AtomicExpand.
This commit is contained in:
Matt Arsenault
parent
7c71ce97e7
commit
df29ec2f54
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@ -898,6 +898,10 @@ defm BUFFER_LOAD_DWORDX4 : MUBUF_Pseudo_Loads <
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"buffer_load_dwordx4", v4i32
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>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, atomic_load_8_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i32, atomic_load_16_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i16, atomic_load_8_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_USHORT", i16, atomic_load_16_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, extloadi8_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_UBYTE", i32, zextloadi8_global>;
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defm : MUBUF_Pseudo_Load_Pats<"BUFFER_LOAD_SBYTE", i32, sextloadi8_global>;
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@ -1794,6 +1798,10 @@ multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo In
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>;
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}
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let SubtargetPredicate = isGFX6GFX7 in {
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_BYTE_ADDR64, BUFFER_STORE_BYTE_OFFSET, i32, atomic_store_global_8>;
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_BYTE_ADDR64, BUFFER_STORE_BYTE_OFFSET, i16, atomic_store_global_8>;
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_SHORT_ADDR64, BUFFER_STORE_SHORT_OFFSET, i32, atomic_store_global_16>;
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_SHORT_ADDR64, BUFFER_STORE_SHORT_OFFSET, i16, atomic_store_global_16>;
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, atomic_store_global_32>;
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defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, atomic_store_global_64>;
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} // End Predicates = isGFX6GFX7
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@ -1089,6 +1089,10 @@ class ScratchLoadSVaddrPat_D16 <FLAT_Pseudo inst, SDPatternOperator node, ValueT
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let OtherPredicates = [HasFlatAddressSpace] in {
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def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i32>;
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def : FlatLoadPat <FLAT_LOAD_UBYTE, atomic_load_8_flat, i16>;
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def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i32>;
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def : FlatLoadPat <FLAT_LOAD_USHORT, atomic_load_16_flat, i16>;
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def : FlatLoadPat <FLAT_LOAD_UBYTE, extloadi8_flat, i32>;
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def : FlatLoadPat <FLAT_LOAD_UBYTE, zextloadi8_flat, i32>;
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def : FlatLoadPat <FLAT_LOAD_SBYTE, sextloadi8_flat, i32>;
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@ -1126,6 +1130,11 @@ def : FlatStorePat <FLAT_STORE_DWORDX4, store_flat, vt>;
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def : FlatStoreAtomicPat <FLAT_STORE_DWORD, atomic_store_flat_32, i32>;
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def : FlatStoreAtomicPat <FLAT_STORE_DWORDX2, atomic_store_flat_64, i64>;
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def : FlatStoreAtomicPat <FLAT_STORE_BYTE, atomic_store_flat_8, i32>;
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def : FlatStoreAtomicPat <FLAT_STORE_BYTE, atomic_store_flat_8, i16>;
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def : FlatStoreAtomicPat <FLAT_STORE_SHORT, atomic_store_flat_16, i32>;
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def : FlatStoreAtomicPat <FLAT_STORE_SHORT, atomic_store_flat_16, i16>;
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foreach as = [ "flat", "global" ] in {
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defm : FlatAtomicPat <"FLAT_ATOMIC_ADD", "atomic_load_add_"#as, i32>;
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@ -1310,6 +1319,10 @@ multiclass ScratchFLATLoadPats_D16<FLAT_Pseudo inst, SDPatternOperator node, Val
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let OtherPredicates = [HasFlatGlobalInsts] in {
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i32>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, atomic_load_8_global, i16>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i32>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_USHORT, atomic_load_16_global, i16>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, extloadi8_global, i32>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_UBYTE, zextloadi8_global, i32>;
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defm : GlobalFLATLoadPats <GLOBAL_LOAD_SBYTE, sextloadi8_global, i32>;
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@ -1369,6 +1382,10 @@ defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_SHORT_D16, load_d16_lo_global, v2i16>
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defm : GlobalFLATLoadPats_D16 <GLOBAL_LOAD_SHORT_D16, load_d16_lo_global, v2f16>;
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}
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_BYTE, atomic_store_global_8, i32>;
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_BYTE, atomic_store_global_8, i16>;
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_SHORT, atomic_store_global_16, i32>;
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_SHORT, atomic_store_global_16, i16>;
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_DWORD, atomic_store_global_32, i32>;
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defm : GlobalFLATAtomicStorePats <GLOBAL_STORE_DWORDX2, atomic_store_global_64, i64>;
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@ -1128,3 +1128,149 @@ entry:
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store atomic float %in, float* %ptr seq_cst, align 4
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i8_offset:
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; CIVI: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; GFX9: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
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; GCN: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i8_offset(i8* %in, i8* %out) {
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entry:
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%gep = getelementptr i8, i8* %in, i64 16
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%val = load atomic i8, i8* %gep seq_cst, align 1
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store i8 %val, i8* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i8:
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; GCN: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
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; GCN: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i8(i8* %in, i8* %out) {
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entry:
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%val = load atomic i8, i8* %in seq_cst, align 1
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store i8 %val, i8* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i8_addr64_offset:
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; CIVI: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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; GFX9: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
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; GCN: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i8_addr64_offset(i8* %in, i8* %out, i64 %index) {
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entry:
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%ptr = getelementptr i8, i8* %in, i64 %index
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%gep = getelementptr i8, i8* %ptr, i64 16
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%val = load atomic i8, i8* %gep seq_cst, align 1
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store i8 %val, i8* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i8_offset:
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; CIVI: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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; GFX9: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_i8_offset(i8 %in, i8* %out) {
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entry:
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%gep = getelementptr i8, i8* %out, i64 16
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store atomic i8 %in, i8* %gep seq_cst, align 1
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i8:
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; GCN: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @atomic_store_i8(i8 %in, i8* %out) {
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entry:
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store atomic i8 %in, i8* %out seq_cst, align 1
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i8_addr64_offset:
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; CIVI: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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; GFX9: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_i8_addr64_offset(i8 %in, i8* %out, i64 %index) {
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entry:
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%ptr = getelementptr i8, i8* %out, i64 %index
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%gep = getelementptr i8, i8* %ptr, i64 16
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store atomic i8 %in, i8* %gep seq_cst, align 1
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i16_offset:
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; CIVI: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; GFX9: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
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; GCN: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i16_offset(i16* %in, i16* %out) {
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entry:
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%gep = getelementptr i16, i16* %in, i64 8
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%val = load atomic i16, i16* %gep seq_cst, align 2
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store i16 %val, i16* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i16:
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; GCN: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
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; GCN: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i16(i16* %in, i16* %out) {
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entry:
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%val = load atomic i16, i16* %in seq_cst, align 2
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store i16 %val, i16* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i16_addr64_offset:
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; CIVI: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
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; GFX9: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
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; GCN: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
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define amdgpu_kernel void @atomic_load_i16_addr64_offset(i16* %in, i16* %out, i64 %index) {
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entry:
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%ptr = getelementptr i16, i16* %in, i64 %index
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%gep = getelementptr i16, i16* %ptr, i64 8
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%val = load atomic i16, i16* %gep seq_cst, align 2
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store i16 %val, i16* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i16_offset:
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; CIVI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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; GFX9: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_i16_offset(i16 %in, i16* %out) {
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entry:
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%gep = getelementptr i16, i16* %out, i64 8
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store atomic i16 %in, i16* %gep seq_cst, align 2
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i16:
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; GCN: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @atomic_store_i16(i16 %in, i16* %out) {
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entry:
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store atomic i16 %in, i16* %out seq_cst, align 2
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i16_addr64_offset:
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; CIVI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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; GFX9: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_i16_addr64_offset(i16 %in, i16* %out, i64 %index) {
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entry:
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%ptr = getelementptr i16, i16* %out, i64 %index
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%gep = getelementptr i16, i16* %ptr, i64 8
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store atomic i16 %in, i16* %gep seq_cst, align 2
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_f16_offset:
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; CIVI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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; GFX9: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_f16_offset(half %in, half* %out) {
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entry:
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%gep = getelementptr half, half* %out, i64 8
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store atomic half %in, half* %gep seq_cst, align 2
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_f16:
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; GCN: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
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define amdgpu_kernel void @atomic_store_f16(half %in, half* %out) {
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entry:
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store atomic half %in, half* %out seq_cst, align 2
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ret void
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}
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@ -1316,3 +1316,124 @@ entry:
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store atomic float %in, float addrspace(1)* %ptr seq_cst, align 4
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i8_offset:
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; SIVI: buffer_load_ubyte [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
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; SIVI: buffer_store_byte [[RET]]
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; GFX9: global_load_ubyte [[RET:v[0-9]+]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
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define amdgpu_kernel void @atomic_load_i8_offset(i8 addrspace(1)* %in, i8 addrspace(1)* %out) {
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entry:
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%gep = getelementptr i8, i8 addrspace(1)* %in, i64 16
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%val = load atomic i8, i8 addrspace(1)* %gep seq_cst, align 1
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store i8 %val, i8 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i8_negoffset:
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; SI: buffer_load_ubyte [[RET:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
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; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xfffffe00
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; VI-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, -1
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; VI: flat_load_ubyte [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
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; GFX9: global_load_ubyte [[RET:v[0-9]+]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:-512 glc{{$}}
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define amdgpu_kernel void @atomic_load_i8_negoffset(i8 addrspace(1)* %in, i8 addrspace(1)* %out) {
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entry:
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%gep = getelementptr i8, i8 addrspace(1)* %in, i64 -512
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%val = load atomic i8, i8 addrspace(1)* %gep seq_cst, align 1
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store i8 %val, i8 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i8_offset:
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; SI: buffer_store_byte {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
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; VI: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
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; GFX9: global_store_byte {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:16{{$}}
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define amdgpu_kernel void @atomic_store_i8_offset(i8 %in, i8 addrspace(1)* %out) {
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entry:
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%gep = getelementptr i8, i8 addrspace(1)* %out, i64 16
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store atomic i8 %in, i8 addrspace(1)* %gep seq_cst, align 1
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ret void
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}
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; GCN-LABEL: {{^}}atomic_store_i8:
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; SI: buffer_store_byte {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
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; VI: flat_store_byte v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
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; GFX9: global_store_byte {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
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define amdgpu_kernel void @atomic_store_i8(i8 %in, i8 addrspace(1)* %out) {
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entry:
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store atomic i8 %in, i8 addrspace(1)* %out seq_cst, align 1
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i16_offset:
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; SIVI: buffer_load_ushort [[RET:v[0-9]+]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16 glc{{$}}
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; SIVI: buffer_store_short [[RET]]
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; GFX9: global_load_ushort [[RET:v[0-9]+]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
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define amdgpu_kernel void @atomic_load_i16_offset(i16 addrspace(1)* %in, i16 addrspace(1)* %out) {
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entry:
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%gep = getelementptr i16, i16 addrspace(1)* %in, i64 8
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%val = load atomic i16, i16 addrspace(1)* %gep seq_cst, align 2
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store i16 %val, i16 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}atomic_load_i16_negoffset:
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; SI: buffer_load_ushort [[RET:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+}}:{{[0-9]+}}], 0 addr64 glc{{$}}
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; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xfffffe00
|
||||
; VI-NEXT: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, -1
|
||||
; VI: flat_load_ushort [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
|
||||
|
||||
; GFX9: global_load_ushort [[RET:v[0-9]+]], v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}] offset:-512 glc{{$}}
|
||||
define amdgpu_kernel void @atomic_load_i16_negoffset(i16 addrspace(1)* %in, i16 addrspace(1)* %out) {
|
||||
entry:
|
||||
%gep = getelementptr i16, i16 addrspace(1)* %in, i64 -256
|
||||
%val = load atomic i16, i16 addrspace(1)* %gep seq_cst, align 2
|
||||
store i16 %val, i16 addrspace(1)* %out
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}atomic_store_i16_offset:
|
||||
; SI: buffer_store_short {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
|
||||
; VI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
|
||||
; GFX9: global_store_short {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:16{{$}}
|
||||
define amdgpu_kernel void @atomic_store_i16_offset(i16 %in, i16 addrspace(1)* %out) {
|
||||
entry:
|
||||
%gep = getelementptr i16, i16 addrspace(1)* %out, i64 8
|
||||
store atomic i16 %in, i16 addrspace(1)* %gep seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}atomic_store_i16:
|
||||
; SI: buffer_store_short {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
|
||||
; VI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
|
||||
; GFX9: global_store_short {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
|
||||
define amdgpu_kernel void @atomic_store_i16(i16 %in, i16 addrspace(1)* %out) {
|
||||
entry:
|
||||
store atomic i16 %in, i16 addrspace(1)* %out seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}atomic_store_f16_offset:
|
||||
; SI: buffer_store_short {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}}
|
||||
; VI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
|
||||
; GFX9: global_store_short {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:16{{$}}
|
||||
define amdgpu_kernel void @atomic_store_f16_offset(half %in, half addrspace(1)* %out) {
|
||||
entry:
|
||||
%gep = getelementptr half, half addrspace(1)* %out, i64 8
|
||||
store atomic half %in, half addrspace(1)* %gep seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}atomic_store_f16:
|
||||
; SI: buffer_store_short {{v[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0{{$}}
|
||||
; VI: flat_store_short v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+$}}
|
||||
; GFX9: global_store_short {{v[0-9]+}}, {{v[0-9]+}}, s{{\[[0-9]+:[0-9]+\]$}}
|
||||
define amdgpu_kernel void @atomic_store_f16(half %in, half addrspace(1)* %out) {
|
||||
entry:
|
||||
store atomic half %in, half addrspace(1)* %out seq_cst, align 2
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue