forked from OSchip/llvm-project
[X86][Haswell][SchedModel] Add architecture specific scheduling models.
Group: Integer instructions. Sub-group: Arithmetic instructions. <rdar://problem/15607571> llvm-svn: 215905
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35d37b7571
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@ -55,6 +55,7 @@ def HWPort06 : ProcResGroup<[HWPort0, HWPort6]>;
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def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>;
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def HWPort16 : ProcResGroup<[HWPort1, HWPort6]>;
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def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>;
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def HWPort056: ProcResGroup<[HWPort0, HWPort5, HWPort6]>;
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def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>;
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// 60 Entry Unified Scheduler
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@ -281,6 +282,21 @@ def Write2P237_P4 : SchedWriteRes<[HWPort237, HWPort4]> {
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def WriteP06 : SchedWriteRes<[HWPort06]>;
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def WriteP0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
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let Latency = 1;
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let ResourceCycles = [1, 2, 1];
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}
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def Write2P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
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let Latency = 1;
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let ResourceCycles = [2, 2, 1];
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}
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def Write3P0156_2P237_P4 : SchedWriteRes<[HWPort0156, HWPort237, HWPort4]> {
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let Latency = 1;
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let ResourceCycles = [3, 2, 1];
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}
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// Notation:
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// - r: register.
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// - mm: 64 bit mmx register.
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@ -406,4 +422,180 @@ def WriteMoveBE64mr : SchedWriteRes<[HWPort06, HWPort15, HWPort237, HWPort4]> {
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}
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def : InstRW<[WriteMoveBE64mr], (instregex "MOVBE64mr")>;
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//-- Arithmetic instructions --//
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// ADD SUB.
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// m,r/i.
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def : InstRW<[Write2P0156_2P237_P4],
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(instregex "(ADD|SUB)(8|16|32|64)m(r|i)",
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"(ADD|SUB)(8|16|32|64)mi8", "(ADD|SUB)64mi32")>;
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// ADC SBB.
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// r,r/i.
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def : InstRW<[Write2P0156_Lat2], (instregex "(ADC|SBB)(8|16|32|64)r(r|i)",
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"(ADC|SBB)(16|32|64)ri8",
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"(ADC|SBB)64ri32",
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"(ADC|SBB)(8|16|32|64)rr_REV")>;
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// r,m.
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def : InstRW<[Write2P0156_Lat2Ld, ReadAfterLd], (instregex "(ADC|SBB)(8|16|32|64)rm")>;
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// m,r/i.
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def : InstRW<[Write3P0156_2P237_P4],
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(instregex "(ADC|SBB)(8|16|32|64)m(r|i)",
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"(ADC|SBB)(16|32|64)mi8",
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"(ADC|SBB)64mi32")>;
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// INC DEC NOT NEG.
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// m.
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def : InstRW<[WriteP0156_2P237_P4],
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(instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m",
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"(INC|DEC)64(16|32)m")>;
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// MUL IMUL.
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// r16.
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def WriteMul16 : SchedWriteRes<[HWPort1, HWPort0156]> {
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let Latency = 4;
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let NumMicroOps = 4;
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}
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def : InstRW<[WriteMul16], (instregex "IMUL16r", "MUL16r")>;
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// m16.
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def WriteMul16Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
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let Latency = 8;
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let NumMicroOps = 5;
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}
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def : InstRW<[WriteMul16Ld], (instregex "IMUL16m", "MUL16m")>;
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// r32.
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def WriteMul32 : SchedWriteRes<[HWPort1, HWPort0156]> {
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let Latency = 4;
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteMul32], (instregex "IMUL32r", "MUL32r")>;
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// m32.
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def WriteMul32Ld : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
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let Latency = 8;
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let NumMicroOps = 4;
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}
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def : InstRW<[WriteMul32Ld], (instregex "IMUL32m", "MUL32m")>;
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// r64.
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def WriteMul64 : SchedWriteRes<[HWPort1, HWPort6]> {
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let Latency = 3;
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let NumMicroOps = 2;
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}
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def : InstRW<[WriteMul64], (instregex "IMUL64r", "MUL64r")>;
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// m64.
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def WriteMul64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
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let Latency = 7;
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteMul64Ld], (instregex "IMUL64m", "MUL64m")>;
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// r16,r16.
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def WriteMul16rri : SchedWriteRes<[HWPort1, HWPort0156]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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def : InstRW<[WriteMul16rri], (instregex "IMUL16rri", "IMUL16rri8")>;
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// r16,m16.
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def WriteMul16rmi : SchedWriteRes<[HWPort1, HWPort0156, HWPort23]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteMul16rmi], (instregex "IMUL16rmi", "IMUL16rmi8")>;
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// MULX.
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// r32,r32,r32.
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def WriteMulX32 : SchedWriteRes<[HWPort1, HWPort056]> {
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let Latency = 4;
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let NumMicroOps = 3;
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let ResourceCycles = [1, 2];
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}
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def : InstRW<[WriteMulX32], (instregex "MULX32rr")>;
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// r32,r32,m32.
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def WriteMulX32Ld : SchedWriteRes<[HWPort1, HWPort056, HWPort23]> {
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let Latency = 8;
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let NumMicroOps = 4;
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let ResourceCycles = [1, 2, 1];
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}
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def : InstRW<[WriteMulX32Ld], (instregex "MULX32rm")>;
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// r64,r64,r64.
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def WriteMulX64 : SchedWriteRes<[HWPort1, HWPort6]> {
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let Latency = 4;
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let NumMicroOps = 2;
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}
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def : InstRW<[WriteMulX64], (instregex "MULX64rr")>;
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// r64,r64,m64.
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def WriteMulX64Ld : SchedWriteRes<[HWPort1, HWPort6, HWPort23]> {
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let Latency = 8;
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteMulX64Ld], (instregex "MULX64rm")>;
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// DIV.
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// r8.
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def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 22;
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let NumMicroOps = 9;
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}
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def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
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// r16.
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def WriteDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 23;
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let NumMicroOps = 10;
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}
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def : InstRW<[WriteDiv16], (instregex "DIV16r")>;
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// r32.
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def WriteDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 22;
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let NumMicroOps = 10;
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}
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def : InstRW<[WriteDiv32], (instregex "DIV32r")>;
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// r64.
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def WriteDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 32;
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let NumMicroOps = 36;
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}
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def : InstRW<[WriteDiv64], (instregex "DIV64r")>;
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// IDIV.
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// r8.
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def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 23;
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let NumMicroOps = 9;
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}
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def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
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// r16.
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def WriteIDiv16 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 23;
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let NumMicroOps = 10;
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}
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def : InstRW<[WriteIDiv16], (instregex "IDIV16r")>;
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// r32.
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def WriteIDiv32 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 22;
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let NumMicroOps = 9;
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}
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def : InstRW<[WriteIDiv32], (instregex "IDIV32r")>;
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// r64.
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def WriteIDiv64 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 39;
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let NumMicroOps = 59;
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}
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def : InstRW<[WriteIDiv64], (instregex "IDIV64r")>;
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} // SchedModel
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