forked from OSchip/llvm-project
[ARM] Remove unused tblgen arguments. NFC
As per D109359, this removes or makes use of some of the existing unused NEON and base ARM tblgn arguments.
This commit is contained in:
David Green
parent
14afbe9448
commit
deefeffb5d
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@ -1589,7 +1589,7 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc,
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let TwoOperandAliasConstraint = "$Rn = $Rd" in
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multiclass AsI1_rbin_irs<bits<4> opcod, string opc,
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InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
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SDNode opnode, bit Commutable = 0> {
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SDNode opnode> {
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// The register-immediate version is re-materializable. This is useful
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// in particular for taking the address of a local.
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let isReMaterializable = 1 in {
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@ -1693,9 +1693,8 @@ multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
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/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
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/// operands are reversed.
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let hasPostISelHook = 1, Defs = [CPSR] in {
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multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
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InstrItinClass iis, SDNode opnode,
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bit Commutable = 0> {
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multiclass AsI1_rbin_s_is<InstrItinClass iii,
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InstrItinClass iis, SDNode opnode> {
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def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
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4, iii,
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[(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
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@ -3853,7 +3852,7 @@ defm RSB : AsI1_rbin_irs<0b0011, "rsb",
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// FIXME: Eliminate them if we can write def : Pat patterns which defines
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// CPSR and the implicit def of CPSR is not needed.
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defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr, ARMsubc>;
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defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUsr, ARMsubc>;
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defm RSC : AI1_rsc_irs<0b0111, "rsc", ARMsube>;
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@ -2735,8 +2735,11 @@ class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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string Dt, ValueType ResTy, ValueType OpTy,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
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(outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin, OpcodeStr, Dt,
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[(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
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let isCommutable = Commutable;
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}
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class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
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@ -2789,19 +2792,22 @@ class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
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let isCommutable = Commutable;
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}
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// Same as N3VQIntnp but with Vd as a src register.
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class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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bit op4, Format f, InstrItinClass itin, string OpcodeStr,
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string Dt, ValueType ResTy, ValueType OpTy,
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SDPatternOperator IntOp, bit Commutable>
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SDPatternOperator IntOp>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm),
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f, itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
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(OpTy QPR:$Vm))))]> {
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let Constraints = "$src = $Vd";
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let isCommutable = 0;
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}
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class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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@ -3118,7 +3124,10 @@ class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
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SDPatternOperator IntOp, bit Commutable>
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: N3Vnp<op27_23, op21_20, op11_8, op6, op4,
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(outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
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[(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
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[(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
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let isCommutable = Commutable;
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}
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class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
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string OpcodeStr, string Dt,
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@ -4041,7 +4050,7 @@ multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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}
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multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
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InstrItinClass itin, string OpcodeStr, string Dt,
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string baseOpc, SDNode OpNode> {
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SDNode OpNode> {
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// 64-bit vector types.
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def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
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OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
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@ -4987,7 +4996,7 @@ class BaseN3VCP8ComplexTiedLane64<bit op4, bit s, bit q, InstrItinClass itin,
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}
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multiclass N3VCP8ComplexTied<bit op21, bit op4,
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string OpcodeStr, SDPatternOperator Op> {
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string OpcodeStr> {
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let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
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def v4f16 : BaseN3VCP8ComplexTied<op21, op4, 0, 0, IIC_VMACD, (outs DPR:$Vd),
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(ins DPR:$src1, DPR:$Vn, DPR:$Vm, complexrotateop:$rot),
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@ -5007,7 +5016,7 @@ multiclass N3VCP8ComplexTied<bit op21, bit op4,
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}
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multiclass N3VCP8ComplexOdd<bit op23, bit op21, bit op4,
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string OpcodeStr, SDPatternOperator Op> {
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string OpcodeStr> {
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let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
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def v4f16 : BaseN3VCP8ComplexOdd<op23, op21, op4, 0, 0, IIC_VMACD,
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(outs DPR:$Vd),
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@ -5032,8 +5041,7 @@ multiclass N3VCP8ComplexOdd<bit op23, bit op21, bit op4,
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// These instructions index by pairs of lanes, so the VectorIndexes are twice
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// as wide as the data types.
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multiclass N3VCP8ComplexTiedLane<bit op4, string OpcodeStr,
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SDPatternOperator Op> {
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multiclass N3VCP8ComplexTiedLane<bit op4, string OpcodeStr> {
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let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
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def v4f16_indexed : BaseN3VCP8ComplexTiedLane32<op4, 0, 0, IIC_VMACD,
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(outs DPR:$Vd),
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@ -5060,9 +5068,9 @@ multiclass N3VCP8ComplexTiedLane<bit op4, string OpcodeStr,
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}
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}
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defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla", null_frag>;
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defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd", null_frag>;
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defm VCMLA : N3VCP8ComplexTiedLane<0, "vcmla", null_frag>;
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defm VCMLA : N3VCP8ComplexTied<1, 0, "vcmla">;
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defm VCADD : N3VCP8ComplexOdd<1, 0, 0, "vcadd">;
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defm VCMLA : N3VCP8ComplexTiedLane<0, "vcmla">;
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let Predicates = [HasNEON,HasV8_3a,HasFullFP16] in {
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def : Pat<(v4f16 (int_arm_neon_vcadd_rot90 (v4f16 DPR:$Rn), (v4f16 DPR:$Rm))),
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@ -5991,9 +5999,9 @@ def : Pat<(v2i64 (ARMvshlu (v2i64 QPR:$Dn), (v2i64 QPR:$Dm))),
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defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", ARMvshlImm>;
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// VSHR : Vector Shift Right (Immediate)
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defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
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defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",
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ARMvshrsImm>;
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defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
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defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",
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ARMvshruImm>;
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// VSHLL : Vector Shift Left Long
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@ -6061,9 +6069,9 @@ defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
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IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
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"vrshl", "u", int_arm_neon_vrshiftu>;
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// VRSHR : Vector Rounding Shift Right
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defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
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defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",
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NEONvrshrsImm>;
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defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
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defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",
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NEONvrshruImm>;
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// VRSHRN : Vector Rounding Shift Right and Narrow
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@ -7074,7 +7082,7 @@ class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
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class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
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: N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
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(ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
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(ins QPR:$Vn, QPR:$Vm, immTy:$index), NVExtFrm,
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IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
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[(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
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(Ty QPR:$Vm), imm:$index)))]> {
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@ -7337,7 +7345,7 @@ let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
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!strconcat("sha", op), "32", v4i32, v4i32, Int>;
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class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
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: N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
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!strconcat("sha", op), "32", v4i32, v4i32, Int, 0>;
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!strconcat("sha", op), "32", v4i32, v4i32, Int>;
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}
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let Predicates = [HasV8, HasAES] in {
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