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Revert "[LiveIntervals] Fix repairOldRegInRange for simple def cases" 

This reverts commit 8229cb7412.

It was failing on buildbots with expensive checks enabled.
This commit is contained in:
Jay Foad 2021-09-23 17:55:05 +01:00
parent bbc74a11bc
commit deb2ca566a
5 changed files with 8 additions and 34 deletions
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15
llvm/lib/CodeGen/LiveIntervals.cpp
View File

@ -1571,14 +1571,15 @@ void LiveIntervals::repairOldRegInRange(const MachineBasicBlock::iterator Begin,
LaneBitmask LaneMask) {
LiveInterval::iterator LII = LR.find(EndIdx);
SlotIndex lastUseIdx;
if (LII != LR.end() && LII->start < EndIdx) {
lastUseIdx = LII->end;
} else if (LII == LR.begin()) {
// We may not have a liverange at all if this is a subregister untouched
// between \p Begin and \p End.
} else {
--LII;
if (LII == LR.begin()) {
// This happens when the function is called for a subregister that only
// occurs _after_ the range that is to be repaired.
return;
}
if (LII != LR.end() && LII->start < EndIdx)
lastUseIdx = LII->end;
else
--LII;
for (MachineBasicBlock::iterator I = End; I != Begin;) {
--I;

1
llvm/test/CodeGen/AMDGPU/extract-load-i1.ll
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@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -early-live-intervals < %s | FileCheck %s
; FIXME: Inefficient codegen which skips an optimization of load +
; extractelement when the vector element type is not byte-sized.

24
llvm/test/CodeGen/AMDGPU/twoaddr-regsequence.mir
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@ -1,24 +0,0 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=liveintervals,twoaddressinstruction,simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck %s
# Check that LiveIntervals are correctly updated when eliminating REG_SEQUENCE.
---
name: f
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: f
; CHECK: liveins: $vgpr0, $vgpr1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: undef %2.sub0:vreg_64 = COPY $vgpr0
; CHECK-NEXT: %2.sub1:vreg_64 = COPY $vgpr1
; CHECK-NEXT: $vgpr2_vgpr3 = COPY %2
; CHECK-NEXT: S_NOP 0, implicit $vgpr2_vgpr3
%0:vgpr_32 = COPY $vgpr0
%1:vgpr_32 = COPY $vgpr1
%35:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
$vgpr2_vgpr3 = COPY %35
S_NOP 0, implicit $vgpr2_vgpr3
...

1
llvm/test/CodeGen/ARM/signext-inreg.ll
View File

@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=armv8 | FileCheck %s
; RUN: llc < %s -mtriple=armv8 -early-live-intervals | FileCheck %s
define <4 x i32> @test(<4 x i32> %m) {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry

1
llvm/test/CodeGen/X86/mul-shift-reassoc.ll
View File

@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: llc < %s -mtriple=i686-- -early-live-intervals | FileCheck %s
define i32 @test(i32 %X, i32 %Y) {
; Push the shl through the mul to allow an LEA to be formed, instead