forked from OSchip/llvm-project
Rename the existing tBX/tBXr9 instructions to tBX_CALL/tBXr9_CALL to better
reflect their actual meaning and match the ARM instructions. llvm-svn: 132039
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@ -1875,7 +1875,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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case ARM::TAILJMPr:
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case ARM::tTAILJMPr: {
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unsigned newOpc = (Opc == ARM::TAILJMPr || Opc == ARM::TAILJMPrND)
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? ARM::BX : ARM::tBX;
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? ARM::BX : ARM::tBX_CALL;
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MCInst TmpInst;
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TmpInst.setOpcode(newOpc);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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@ -466,7 +466,7 @@ let isCall = 1,
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// ARMv4T
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// FIXME: Should be a pseudo.
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let isCodeGenOnly = 1 in
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def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
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def tBX_CALL : TIx2<{?,?,?,?,?}, {?,?}, ?,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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@ -521,7 +521,7 @@ let isCall = 1,
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// ARMv4T
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let isCodeGenOnly = 1 in
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// FIXME: Should be a pseudo.
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def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
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def tBXr9_CALL : TIx2<{?,?,?,?,?}, {?,?}, ?,
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(outs), (ins tGPR:$func, variable_ops), IIC_Br,
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"mov\tlr, pc\n\tbx\t$func",
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[(ARMcall_nolink tGPR:$func)]>,
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