forked from OSchip/llvm-project
AMDGPU: Add baseline test for incorrect SP access
This commit is contained in:
Matt Arsenault
parent
8d8a496356
commit
deae5e567d
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
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; Make sure we use the correct frame offset is used with the local
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; frame area.
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;
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; %pin.low is allocated to offset 0.
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;
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; %local.area is assigned to the local frame offset by the
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; LocalStackSlotAllocation pass at offset 4096.
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;
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; The %load1 access to %gep.large.offset initially used the stack
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; pointer register and directly referenced the frame index. After
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; LocalStackSlotAllocation, it would no longer refer to a frame index
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; so eliminateFrameIndex would not adjust the access to use the
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; correct FP offset.
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define amdgpu_kernel void @local_stack_offset_uses_sp(i64 addrspace(1)* %out, i8 addrspace(1)* %in) {
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; GCN-LABEL: local_stack_offset_uses_sp:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
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; GCN-NEXT: s_add_u32 flat_scratch_lo, s6, s9
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; GCN-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
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; GCN-NEXT: s_add_u32 s0, s0, s9
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; GCN-NEXT: v_mov_b32_e32 v1, 0x3000
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; GCN-NEXT: s_addc_u32 s1, s1, 0
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; GCN-NEXT: v_add_u32_e32 v0, 64, v1
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; GCN-NEXT: v_mov_b32_e32 v2, 0
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; GCN-NEXT: v_mov_b32_e32 v3, 0x2000
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; GCN-NEXT: s_mov_b32 s6, 0
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; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
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; GCN-NEXT: BB0_1: ; %loadstoreloop
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_add_u32_e32 v3, s6, v1
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; GCN-NEXT: s_add_i32 s6, s6, 1
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; GCN-NEXT: s_cmpk_lt_u32 s6, 0x2120
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; GCN-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen
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; GCN-NEXT: s_cbranch_scc1 BB0_1
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; GCN-NEXT: ; %bb.2: ; %split
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; GCN-NEXT: v_mov_b32_e32 v1, 0x3000
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; GCN-NEXT: v_add_u32_e32 v1, 0x20d0, v1
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; GCN-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen
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; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4
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; GCN-NEXT: buffer_load_dword v3, v0, s[0:3], s32 offen
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; GCN-NEXT: buffer_load_dword v4, v0, s[0:3], s32 offen offset:4
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; GCN-NEXT: s_waitcnt vmcnt(1)
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; GCN-NEXT: v_add_co_u32_e32 v0, vcc, v2, v3
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v2, s4
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
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; GCN-NEXT: v_mov_b32_e32 v3, s5
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; GCN-NEXT: global_store_dwordx2 v[2:3], v[0:1], off
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; GCN-NEXT: s_endpgm
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entry:
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%pin.low = alloca i32, align 8192, addrspace(5)
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%local.area = alloca [1060 x i64], align 4096, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %pin.low
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%local.area.cast = bitcast [1060 x i64] addrspace(5)* %local.area to i8 addrspace(5)*
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call void @llvm.memset.p5i8.i32(i8 addrspace(5)* align 4 %local.area.cast, i8 0, i32 8480, i1 true)
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%gep.large.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 1050
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%gep.small.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 8
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%load0 = load volatile i64, i64 addrspace(5)* %gep.large.offset
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%load1 = load volatile i64, i64 addrspace(5)* %gep.small.offset
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%add0 = add i64 %load0, %load1
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store volatile i64 %add0, i64 addrspace(1)* %out
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ret void
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}
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define void @func_local_stack_offset_uses_sp(i64 addrspace(1)* %out, i8 addrspace(1)* %in) {
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; GCN-LABEL: func_local_stack_offset_uses_sp:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: s_add_u32 s4, s32, 0x7ffc0
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; GCN-NEXT: s_mov_b32 s5, s33
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; GCN-NEXT: s_and_b32 s33, s4, 0xfff80000
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; GCN-NEXT: v_lshrrev_b32_e64 v3, 6, s33
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; GCN-NEXT: v_add_u32_e32 v3, 0x1000, v3
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; GCN-NEXT: v_mov_b32_e32 v4, 0
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; GCN-NEXT: v_add_u32_e32 v2, 64, v3
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; GCN-NEXT: s_mov_b32 s4, 0
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; GCN-NEXT: s_add_u32 s32, s32, 0x180000
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; GCN-NEXT: buffer_store_dword v4, off, s[0:3], s33
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; GCN-NEXT: BB1_1: ; %loadstoreloop
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: v_add_u32_e32 v5, s4, v3
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; GCN-NEXT: s_add_i32 s4, s4, 1
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; GCN-NEXT: s_cmpk_lt_u32 s4, 0x2120
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; GCN-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen
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; GCN-NEXT: s_cbranch_scc1 BB1_1
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; GCN-NEXT: ; %bb.2: ; %split
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; GCN-NEXT: v_lshrrev_b32_e64 v3, 6, s33
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; GCN-NEXT: v_add_u32_e32 v3, 0x1000, v3
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; GCN-NEXT: v_add_u32_e32 v3, 0x20d0, v3
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; GCN-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen
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; GCN-NEXT: buffer_load_dword v3, v3, s[0:3], 0 offen offset:4
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; GCN-NEXT: buffer_load_dword v5, v2, s[0:3], s32 offen
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; GCN-NEXT: buffer_load_dword v6, v2, s[0:3], s32 offen offset:4
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; GCN-NEXT: s_sub_u32 s32, s32, 0x180000
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; GCN-NEXT: s_mov_b32 s33, s5
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; GCN-NEXT: s_waitcnt vmcnt(1)
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; GCN-NEXT: v_add_co_u32_e32 v2, vcc, v4, v5
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
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; GCN-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: s_setpc_b64 s[30:31]
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entry:
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%pin.low = alloca i32, align 8192, addrspace(5)
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%local.area = alloca [1060 x i64], align 4096, addrspace(5)
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store volatile i32 0, i32 addrspace(5)* %pin.low
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%local.area.cast = bitcast [1060 x i64] addrspace(5)* %local.area to i8 addrspace(5)*
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call void @llvm.memset.p5i8.i32(i8 addrspace(5)* align 4 %local.area.cast, i8 0, i32 8480, i1 true)
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%gep.large.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 1050
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%gep.small.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 8
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%load0 = load volatile i64, i64 addrspace(5)* %gep.large.offset
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%load1 = load volatile i64, i64 addrspace(5)* %gep.small.offset
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%add0 = add i64 %load0, %load1
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store volatile i64 %add0, i64 addrspace(1)* %out
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ret void
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}
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declare void @llvm.memset.p5i8.i32(i8 addrspace(5)* nocapture writeonly, i8, i32, i1 immarg) #0
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attributes #0 = { argmemonly nounwind willreturn writeonly }
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