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[X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDUP reg-mem instructions 

They shouldn't be treated as pure loads.

Found while investigating D44428

llvm-svn: 327505
This commit is contained in:
Simon Pilgrim 2018-03-14 13:22:56 +00:00
parent 0ee4a08c00
commit de995e6e37
3 changed files with 23 additions and 19 deletions
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9
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -4708,6 +4708,7 @@ let AddedComplexity = 20 in {
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
// SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP // SSE3 - Replicate Single FP - MOVSHDUP and MOVSLDUP
//===---------------------------------------------------------------------===// //===---------------------------------------------------------------------===//
multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr, multiclass sse3_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
ValueType vt, RegisterClass RC, PatFrag mem_frag, ValueType vt, RegisterClass RC, PatFrag mem_frag,
X86MemOperand x86memop> { X86MemOperand x86memop> {
@ -4718,7 +4719,7 @@ def rr : S3SI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src), def rm : S3SI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set RC:$dst, (OpNode (mem_frag addr:$src)))], [(set RC:$dst, (OpNode (mem_frag addr:$src)))],
IIC_SSE_MOV_LH>, Sched<[WriteLoad]>; IIC_SSE_MOV_LH>, Sched<[WriteFShuffleLd]>;
} }
let Predicates = [HasAVX, NoVLX] in { let Predicates = [HasAVX, NoVLX] in {
@ -4786,10 +4787,10 @@ def rm : S3DI<0x12, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
[(set VR128:$dst, [(set VR128:$dst,
(v2f64 (X86Movddup (v2f64 (X86Movddup
(scalar_to_vector (loadf64 addr:$src)))))], (scalar_to_vector (loadf64 addr:$src)))))],
IIC_SSE_MOV_LH>, Sched<[WriteLoad]>; IIC_SSE_MOV_LH>, Sched<[WriteFShuffleLd]>;
} }
// FIXME: Merge with above classe when there're patterns for the ymm version // FIXME: Merge with above classes when there are patterns for the ymm version
multiclass sse3_replicate_dfp_y<string OpcodeStr> { multiclass sse3_replicate_dfp_y<string OpcodeStr> {
def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src), def rr : S3DI<0x12, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
@ -4799,7 +4800,7 @@ def rm : S3DI<0x12, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
[(set VR256:$dst, [(set VR256:$dst,
(v4f64 (X86Movddup (loadv4f64 addr:$src))))]>, (v4f64 (X86Movddup (loadv4f64 addr:$src))))]>,
Sched<[WriteLoad]>; Sched<[WriteFShuffleLd]>;
} }
let Predicates = [HasAVX, NoVLX] in { let Predicates = [HasAVX, NoVLX] in {

6
llvm/test/CodeGen/X86/avx-schedule.ll
View File

@ -2690,7 +2690,7 @@ define <4 x double> @test_movddup(<4 x double> %a0, <4 x double> *%a1) {
; ;
; BTVER2-LABEL: test_movddup: ; BTVER2-LABEL: test_movddup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [5:1.00] ; BTVER2-NEXT: vmovddup {{.*#+}} ymm1 = mem[0,0,2,2] sched: [6:1.00]
; BTVER2-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:0.50] ; BTVER2-NEXT: vmovddup {{.*#+}} ymm0 = ymm0[0,0,2,2] sched: [1:0.50]
; BTVER2-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00] ; BTVER2-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
@ -3030,7 +3030,7 @@ define <8 x float> @test_movshdup(<8 x float> %a0, <8 x float> *%a1) {
; ;
; BTVER2-LABEL: test_movshdup: ; BTVER2-LABEL: test_movshdup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [5:1.00] ; BTVER2-NEXT: vmovshdup {{.*#+}} ymm1 = mem[1,1,3,3,5,5,7,7] sched: [6:1.00]
; BTVER2-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:0.50] ; BTVER2-NEXT: vmovshdup {{.*#+}} ymm0 = ymm0[1,1,3,3,5,5,7,7] sched: [1:0.50]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00] ; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
@ -3093,7 +3093,7 @@ define <8 x float> @test_movsldup(<8 x float> %a0, <8 x float> *%a1) {
; ;
; BTVER2-LABEL: test_movsldup: ; BTVER2-LABEL: test_movsldup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [5:1.00] ; BTVER2-NEXT: vmovsldup {{.*#+}} ymm1 = mem[0,0,2,2,4,4,6,6] sched: [6:1.00]
; BTVER2-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:0.50] ; BTVER2-NEXT: vmovsldup {{.*#+}} ymm0 = ymm0[0,0,2,2,4,4,6,6] sched: [1:0.50]
; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00] ; BTVER2-NEXT: vaddps %ymm1, %ymm0, %ymm0 # sched: [3:2.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]

27
llvm/test/CodeGen/X86/sse3-schedule.ll
View File

@ -563,9 +563,10 @@ define <2 x double> @test_movddup(<2 x double> %a0, <2 x double> *%a1) {
; ;
; SLM-LABEL: test_movddup: ; SLM-LABEL: test_movddup:
; SLM: # %bb.0: ; SLM: # %bb.0:
; SLM-NEXT: movddup {{.*#+}} xmm1 = xmm0[0,0] sched: [1:1.00] ; SLM-NEXT: movddup {{.*#+}} xmm1 = mem[0,0] sched: [4:1.00]
; SLM-NEXT: movddup {{.*#+}} xmm0 = mem[0,0] sched: [3:1.00] ; SLM-NEXT: movddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:1.00]
; SLM-NEXT: subpd %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: subpd %xmm0, %xmm1 # sched: [3:1.00]
; SLM-NEXT: movapd %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movddup: ; SANDY-LABEL: test_movddup:
@ -605,7 +606,7 @@ define <2 x double> @test_movddup(<2 x double> %a0, <2 x double> *%a1) {
; ;
; BTVER2-LABEL: test_movddup: ; BTVER2-LABEL: test_movddup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [5:1.00] ; BTVER2-NEXT: vmovddup {{.*#+}} xmm1 = mem[0,0] sched: [6:1.00]
; BTVER2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:0.50] ; BTVER2-NEXT: vmovddup {{.*#+}} xmm0 = xmm0[0,0] sched: [1:0.50]
; BTVER2-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vsubpd %xmm0, %xmm1, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
@ -641,9 +642,10 @@ define <4 x float> @test_movshdup(<4 x float> %a0, <4 x float> *%a1) {
; ;
; SLM-LABEL: test_movshdup: ; SLM-LABEL: test_movshdup:
; SLM: # %bb.0: ; SLM: # %bb.0:
; SLM-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3] sched: [1:1.00] ; SLM-NEXT: movshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [4:1.00]
; SLM-NEXT: movshdup {{.*#+}} xmm0 = mem[1,1,3,3] sched: [3:1.00] ; SLM-NEXT: movshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:1.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: addps %xmm0, %xmm1 # sched: [3:1.00]
; SLM-NEXT: movaps %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movshdup: ; SANDY-LABEL: test_movshdup:
@ -683,7 +685,7 @@ define <4 x float> @test_movshdup(<4 x float> %a0, <4 x float> *%a1) {
; ;
; BTVER2-LABEL: test_movshdup: ; BTVER2-LABEL: test_movshdup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [5:1.00] ; BTVER2-NEXT: vmovshdup {{.*#+}} xmm1 = mem[1,1,3,3] sched: [6:1.00]
; BTVER2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:0.50] ; BTVER2-NEXT: vmovshdup {{.*#+}} xmm0 = xmm0[1,1,3,3] sched: [1:0.50]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]
@ -719,9 +721,10 @@ define <4 x float> @test_movsldup(<4 x float> %a0, <4 x float> *%a1) {
; ;
; SLM-LABEL: test_movsldup: ; SLM-LABEL: test_movsldup:
; SLM: # %bb.0: ; SLM: # %bb.0:
; SLM-NEXT: movsldup {{.*#+}} xmm1 = xmm0[0,0,2,2] sched: [1:1.00] ; SLM-NEXT: movsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [4:1.00]
; SLM-NEXT: movsldup {{.*#+}} xmm0 = mem[0,0,2,2] sched: [3:1.00] ; SLM-NEXT: movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:1.00]
; SLM-NEXT: addps %xmm1, %xmm0 # sched: [3:1.00] ; SLM-NEXT: addps %xmm0, %xmm1 # sched: [3:1.00]
; SLM-NEXT: movaps %xmm1, %xmm0 # sched: [1:1.00]
; SLM-NEXT: retq # sched: [4:1.00] ; SLM-NEXT: retq # sched: [4:1.00]
; ;
; SANDY-LABEL: test_movsldup: ; SANDY-LABEL: test_movsldup:
@ -761,7 +764,7 @@ define <4 x float> @test_movsldup(<4 x float> %a0, <4 x float> *%a1) {
; ;
; BTVER2-LABEL: test_movsldup: ; BTVER2-LABEL: test_movsldup:
; BTVER2: # %bb.0: ; BTVER2: # %bb.0:
; BTVER2-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [5:1.00] ; BTVER2-NEXT: vmovsldup {{.*#+}} xmm1 = mem[0,0,2,2] sched: [6:1.00]
; BTVER2-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50] ; BTVER2-NEXT: vmovsldup {{.*#+}} xmm0 = xmm0[0,0,2,2] sched: [1:0.50]
; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00] ; BTVER2-NEXT: vaddps %xmm1, %xmm0, %xmm0 # sched: [3:1.00]
; BTVER2-NEXT: retq # sched: [4:1.00] ; BTVER2-NEXT: retq # sched: [4:1.00]