forked from OSchip/llvm-project
Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions. No functional change. llvm-svn: 160037
This commit is contained in:
Nadav Rotem
parent
b8844d6744
commit
de6fd282ef
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@ -70,6 +70,9 @@ private:
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SDValue OptimizeFloatStore(StoreSDNode *ST);
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void LegalizeLoadOps(SDNode *Node);
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void LegalizeStoreOps(SDNode *Node);
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/// PerformInsertVectorEltInMemory - Some target cannot handle a variable
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/// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it
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/// is necessary to spill the vector being inserted into to memory, perform
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@ -689,6 +692,435 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) {
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return SDValue(0, 0);
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}
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void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
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StoreSDNode *ST = cast<StoreSDNode>(Node);
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SDValue Tmp1 = ST->getChain();
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SDValue Tmp2 = ST->getBasePtr();
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DebugLoc dl = Node->getDebugLoc();
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unsigned Alignment = ST->getAlignment();
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bool isVolatile = ST->isVolatile();
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bool isNonTemporal = ST->isNonTemporal();
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if (!ST->isTruncatingStore()) {
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if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
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ReplaceNode(ST, OptStore);
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return;
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}
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{
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SDValue Tmp3 = ST->getValue();
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EVT VT = Tmp3.getValueType();
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switch (TLI.getOperationAction(ISD::STORE, VT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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// If this is an unaligned store and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
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Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
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if (ST->getAlignment() < ABIAlignment)
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ExpandUnalignedStore(cast<StoreSDNode>(Node),
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DAG, TLI, this);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Tmp1.getNode())
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ReplaceNode(SDValue(Node, 0), Tmp1);
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break;
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case TargetLowering::Promote: {
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assert(VT.isVector() && "Unknown legal promote case!");
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Tmp3 = DAG.getNode(ISD::BITCAST, dl,
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TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
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SDValue Result =
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DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
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ST->getPointerInfo(), isVolatile,
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isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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break;
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}
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}
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return;
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}
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} else {
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SDValue Tmp3 = ST->getValue();
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EVT StVT = ST->getMemoryVT();
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unsigned StWidth = StVT.getSizeInBits();
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if (StWidth != StVT.getStoreSizeInBits()) {
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// Promote to a byte-sized store with upper bits zero if not
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// storing an integral number of bytes. For example, promote
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// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
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EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
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StVT.getStoreSizeInBits());
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Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
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SDValue Result =
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DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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NVT, isVolatile, isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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} else if (StWidth & (StWidth - 1)) {
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// If not storing a power-of-2 number of bits, expand as two stores.
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assert(!StVT.isVector() && "Unsupported truncstore!");
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unsigned RoundWidth = 1 << Log2_32(StWidth);
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assert(RoundWidth < StWidth);
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unsigned ExtraWidth = StWidth - RoundWidth;
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assert(ExtraWidth < RoundWidth);
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assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
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"Store size not an integral number of bytes!");
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EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
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EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
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SDValue Lo, Hi;
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unsigned IncrementSize;
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if (TLI.isLittleEndian()) {
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// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
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// Store the bottom RoundWidth bits.
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Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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RoundVT,
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isVolatile, isNonTemporal, Alignment);
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
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DAG.getConstant(RoundWidth,
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TLI.getShiftAmountTy(Tmp3.getValueType())));
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Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
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ST->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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} else {
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// Big endian - avoid unaligned stores.
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// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
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// Store the top RoundWidth bits.
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Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
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DAG.getConstant(ExtraWidth,
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TLI.getShiftAmountTy(Tmp3.getValueType())));
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Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
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RoundVT, isVolatile, isNonTemporal, Alignment);
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// Store the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
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ST->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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}
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// The order of the stores doesn't matter.
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SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
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ReplaceNode(SDValue(Node, 0), Result);
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} else {
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switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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// If this is an unaligned store and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
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Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
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if (ST->getAlignment() < ABIAlignment)
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ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Tmp1.getNode())
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ReplaceNode(SDValue(Node, 0), Tmp1);
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break;
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case TargetLowering::Expand:
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assert(!StVT.isVector() &&
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"Vector Stores are handled in LegalizeVectorOps");
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// TRUNCSTORE:i16 i32 -> STORE i16
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assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
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Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
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SDValue Result =
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DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
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isVolatile, isNonTemporal, Alignment);
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ReplaceNode(SDValue(Node, 0), Result);
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break;
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}
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}
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}
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}
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void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
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LoadSDNode *LD = cast<LoadSDNode>(Node);
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SDValue Tmp1 = LD->getChain(); // Legalize the chain.
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SDValue Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
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DebugLoc dl = Node->getDebugLoc();
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ISD::LoadExtType ExtType = LD->getExtensionType();
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if (ExtType == ISD::NON_EXTLOAD) {
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EVT VT = Node->getValueType(0);
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SDValue Tmp3 = SDValue(Node, 0);
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SDValue Tmp4 = SDValue(Node, 1);
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switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Legal:
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
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if (LD->getAlignment() < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node),
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DAG, TLI, Tmp3, Tmp4);
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}
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}
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break;
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case TargetLowering::Custom:
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Tmp1 = TLI.LowerOperation(Tmp3, DAG);
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if (Tmp1.getNode()) {
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Tmp3 = Tmp1;
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Tmp4 = Tmp1.getValue(1);
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}
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break;
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case TargetLowering::Promote: {
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// Only promote a load of vector type to another.
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assert(VT.isVector() && "Cannot promote this load!");
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// Change base type to a different vector type.
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EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
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Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isInvariant(), LD->getAlignment());
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Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
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Tmp4 = Tmp1.getValue(1);
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break;
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}
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}
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if (Tmp4.getNode() != Node) {
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assert(Tmp3.getNode() != Node && "Load must be completely replaced");
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
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DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
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ReplacedNode(Node);
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}
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return;
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}
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EVT SrcVT = LD->getMemoryVT();
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unsigned SrcWidth = SrcVT.getSizeInBits();
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unsigned Alignment = LD->getAlignment();
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bool isVolatile = LD->isVolatile();
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bool isNonTemporal = LD->isNonTemporal();
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if (SrcWidth != SrcVT.getStoreSizeInBits() &&
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// Some targets pretend to have an i1 loading operation, and actually
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// load an i8. This trick is correct for ZEXTLOAD because the top 7
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// bits are guaranteed to be zero; it helps the optimizers understand
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// that these bits are zero. It is also useful for EXTLOAD, since it
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// tells the optimizers that those bits are undefined. It would be
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// nice to have an effective generic way of getting these benefits...
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// Until such a way is found, don't insist on promoting i1 here.
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(SrcVT != MVT::i1 ||
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TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
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// Promote to a byte-sized load if not loading an integral number of
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// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
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unsigned NewWidth = SrcVT.getStoreSizeInBits();
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EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
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SDValue Ch;
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// The extra bits are guaranteed to be zero, since we stored them that
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// way. A zext load from NVT thus automatically gives zext from SrcVT.
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ISD::LoadExtType NewExtType =
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ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
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SDValue Result =
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DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
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Tmp1, Tmp2, LD->getPointerInfo(),
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NVT, isVolatile, isNonTemporal, Alignment);
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Ch = Result.getValue(1); // The chain.
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if (ExtType == ISD::SEXTLOAD)
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// Having the top bits zero doesn't help when sign extending.
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Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
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Result.getValueType(),
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Result, DAG.getValueType(SrcVT));
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else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
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// All the top bits are guaranteed to be zero - inform the optimizers.
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Result = DAG.getNode(ISD::AssertZext, dl,
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Result.getValueType(), Result,
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DAG.getValueType(SrcVT));
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Tmp1 = Result;
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Tmp2 = Ch;
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} else if (SrcWidth & (SrcWidth - 1)) {
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// If not loading a power-of-2 number of bits, expand as two loads.
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assert(!SrcVT.isVector() && "Unsupported extload!");
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unsigned RoundWidth = 1 << Log2_32(SrcWidth);
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assert(RoundWidth < SrcWidth);
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unsigned ExtraWidth = SrcWidth - RoundWidth;
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assert(ExtraWidth < RoundWidth);
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assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
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"Load size not an integral number of bytes!");
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EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
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EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
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SDValue Lo, Hi, Ch;
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unsigned IncrementSize;
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if (TLI.isLittleEndian()) {
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// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
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// Load the bottom RoundWidth bits.
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
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Tmp1, Tmp2,
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LD->getPointerInfo(), RoundVT, isVolatile,
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isNonTemporal, Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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// Build a factor node to remember that this load is independent of
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// the other one.
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Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Move the top bits to the right place.
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Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
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DAG.getConstant(RoundWidth,
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TLI.getShiftAmountTy(Hi.getValueType())));
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// Join the hi and lo parts.
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Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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} else {
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// Big endian - avoid unaligned loads.
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// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
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// Load the top RoundWidth bits.
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Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
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LD->getPointerInfo(), RoundVT, isVolatile,
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isNonTemporal, Alignment);
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// Load the remaining ExtraWidth bits.
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IncrementSize = RoundWidth / 8;
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Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
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DAG.getIntPtrConstant(IncrementSize));
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Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
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dl, Node->getValueType(0), Tmp1, Tmp2,
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LD->getPointerInfo().getWithOffset(IncrementSize),
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ExtraVT, isVolatile, isNonTemporal,
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MinAlign(Alignment, IncrementSize));
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// Build a factor node to remember that this load is independent of
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// the other one.
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Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
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Hi.getValue(1));
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// Move the top bits to the right place.
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Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
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DAG.getConstant(ExtraWidth,
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TLI.getShiftAmountTy(Hi.getValueType())));
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// Join the hi and lo parts.
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Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
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}
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Tmp2 = Ch;
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} else {
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bool isCustom = false;
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switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
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default: llvm_unreachable("This action is not supported yet!");
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case TargetLowering::Custom:
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isCustom = true;
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// FALLTHROUGH
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case TargetLowering::Legal:
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Tmp1 = SDValue(Node, 0);
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Tmp2 = SDValue(Node, 1);
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if (isCustom) {
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SDValue Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
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if (Tmp3.getNode()) {
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Tmp1 = Tmp3;
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Tmp2 = Tmp3.getValue(1);
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}
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} else {
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// If this is an unaligned load and the target doesn't support it,
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// expand it.
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if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
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Type *Ty =
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LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
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unsigned ABIAlignment =
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TLI.getTargetData()->getABITypeAlignment(Ty);
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if (LD->getAlignment() < ABIAlignment){
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ExpandUnalignedLoad(cast<LoadSDNode>(Node),
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DAG, TLI, Tmp1, Tmp2);
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}
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}
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}
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break;
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case TargetLowering::Expand:
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if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
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SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
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LD->getPointerInfo(),
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LD->isVolatile(), LD->isNonTemporal(),
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LD->isInvariant(), LD->getAlignment());
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unsigned ExtendOp;
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switch (ExtType) {
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case ISD::EXTLOAD:
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ExtendOp = (SrcVT.isFloatingPoint() ?
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ISD::FP_EXTEND : ISD::ANY_EXTEND);
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break;
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case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
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case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
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default: llvm_unreachable("Unexpected extend load type!");
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}
|
||||
Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
|
||||
Tmp2 = Load.getValue(1);
|
||||
break;
|
||||
}
|
||||
|
||||
assert(!SrcVT.isVector() &&
|
||||
"Vector Loads are handled in LegalizeVectorOps");
|
||||
|
||||
// FIXME: This does not work for vectors on most targets. Sign- and
|
||||
// zero-extend operations are currently folded into extending loads,
|
||||
// whether they are legal or not, and then we end up here without any
|
||||
// support for legalizing them.
|
||||
assert(ExtType != ISD::EXTLOAD &&
|
||||
"EXTLOAD should always be supported!");
|
||||
// Turn the unsupported load into an EXTLOAD followed by an explicit
|
||||
// zero/sign extend inreg.
|
||||
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
|
||||
Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->getAlignment());
|
||||
SDValue ValRes;
|
||||
if (ExtType == ISD::SEXTLOAD)
|
||||
ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
|
||||
Result.getValueType(),
|
||||
Result, DAG.getValueType(SrcVT));
|
||||
else
|
||||
ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
|
||||
Tmp1 = ValRes;
|
||||
Tmp2 = Result.getValue(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Since loads produce two values, make sure to remember that we legalized
|
||||
// both of them.
|
||||
if (Tmp2.getNode() != Node) {
|
||||
assert(Tmp1.getNode() != Node && "Load must be completely replaced");
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
|
||||
ReplacedNode(Node);
|
||||
}
|
||||
}
|
||||
|
||||
/// LegalizeOp - Return a legal replacement for the given operation, with
|
||||
/// all legal operands.
|
||||
void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
||||
|
|
@ -710,7 +1142,6 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
|||
"Unexpected illegal type!");
|
||||
|
||||
SDValue Tmp1, Tmp2, Tmp3, Tmp4;
|
||||
bool isCustom = false;
|
||||
|
||||
// Figure out the correct action; the way to query this varies by opcode
|
||||
TargetLowering::LegalizeAction Action = TargetLowering::Legal;
|
||||
|
|
@ -909,429 +1340,10 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
|
|||
case ISD::CALLSEQ_END:
|
||||
break;
|
||||
case ISD::LOAD: {
|
||||
LoadSDNode *LD = cast<LoadSDNode>(Node);
|
||||
Tmp1 = LD->getChain(); // Legalize the chain.
|
||||
Tmp2 = LD->getBasePtr(); // Legalize the base pointer.
|
||||
|
||||
ISD::LoadExtType ExtType = LD->getExtensionType();
|
||||
if (ExtType == ISD::NON_EXTLOAD) {
|
||||
EVT VT = Node->getValueType(0);
|
||||
Tmp3 = SDValue(Node, 0);
|
||||
Tmp4 = SDValue(Node, 1);
|
||||
|
||||
switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
|
||||
default: llvm_unreachable("This action is not supported yet!");
|
||||
case TargetLowering::Legal:
|
||||
// If this is an unaligned load and the target doesn't support it,
|
||||
// expand it.
|
||||
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
|
||||
Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
|
||||
unsigned ABIAlignment = TLI.getTargetData()->getABITypeAlignment(Ty);
|
||||
if (LD->getAlignment() < ABIAlignment){
|
||||
ExpandUnalignedLoad(cast<LoadSDNode>(Node),
|
||||
DAG, TLI, Tmp3, Tmp4);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case TargetLowering::Custom:
|
||||
Tmp1 = TLI.LowerOperation(Tmp3, DAG);
|
||||
if (Tmp1.getNode()) {
|
||||
Tmp3 = Tmp1;
|
||||
Tmp4 = Tmp1.getValue(1);
|
||||
}
|
||||
break;
|
||||
case TargetLowering::Promote: {
|
||||
// Only promote a load of vector type to another.
|
||||
assert(VT.isVector() && "Cannot promote this load!");
|
||||
// Change base type to a different vector type.
|
||||
EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
|
||||
|
||||
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getPointerInfo(),
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->isInvariant(), LD->getAlignment());
|
||||
Tmp3 = DAG.getNode(ISD::BITCAST, dl, VT, Tmp1);
|
||||
Tmp4 = Tmp1.getValue(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (Tmp4.getNode() != Node) {
|
||||
assert(Tmp3.getNode() != Node && "Load must be completely replaced");
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp3);
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp4);
|
||||
ReplacedNode(Node);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
EVT SrcVT = LD->getMemoryVT();
|
||||
unsigned SrcWidth = SrcVT.getSizeInBits();
|
||||
unsigned Alignment = LD->getAlignment();
|
||||
bool isVolatile = LD->isVolatile();
|
||||
bool isNonTemporal = LD->isNonTemporal();
|
||||
|
||||
if (SrcWidth != SrcVT.getStoreSizeInBits() &&
|
||||
// Some targets pretend to have an i1 loading operation, and actually
|
||||
// load an i8. This trick is correct for ZEXTLOAD because the top 7
|
||||
// bits are guaranteed to be zero; it helps the optimizers understand
|
||||
// that these bits are zero. It is also useful for EXTLOAD, since it
|
||||
// tells the optimizers that those bits are undefined. It would be
|
||||
// nice to have an effective generic way of getting these benefits...
|
||||
// Until such a way is found, don't insist on promoting i1 here.
|
||||
(SrcVT != MVT::i1 ||
|
||||
TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
|
||||
// Promote to a byte-sized load if not loading an integral number of
|
||||
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
|
||||
unsigned NewWidth = SrcVT.getStoreSizeInBits();
|
||||
EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
|
||||
SDValue Ch;
|
||||
|
||||
// The extra bits are guaranteed to be zero, since we stored them that
|
||||
// way. A zext load from NVT thus automatically gives zext from SrcVT.
|
||||
|
||||
ISD::LoadExtType NewExtType =
|
||||
ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
|
||||
|
||||
SDValue Result =
|
||||
DAG.getExtLoad(NewExtType, dl, Node->getValueType(0),
|
||||
Tmp1, Tmp2, LD->getPointerInfo(),
|
||||
NVT, isVolatile, isNonTemporal, Alignment);
|
||||
|
||||
Ch = Result.getValue(1); // The chain.
|
||||
|
||||
if (ExtType == ISD::SEXTLOAD)
|
||||
// Having the top bits zero doesn't help when sign extending.
|
||||
Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
|
||||
Result.getValueType(),
|
||||
Result, DAG.getValueType(SrcVT));
|
||||
else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
|
||||
// All the top bits are guaranteed to be zero - inform the optimizers.
|
||||
Result = DAG.getNode(ISD::AssertZext, dl,
|
||||
Result.getValueType(), Result,
|
||||
DAG.getValueType(SrcVT));
|
||||
|
||||
Tmp1 = Result;
|
||||
Tmp2 = Ch;
|
||||
} else if (SrcWidth & (SrcWidth - 1)) {
|
||||
// If not loading a power-of-2 number of bits, expand as two loads.
|
||||
assert(!SrcVT.isVector() && "Unsupported extload!");
|
||||
unsigned RoundWidth = 1 << Log2_32(SrcWidth);
|
||||
assert(RoundWidth < SrcWidth);
|
||||
unsigned ExtraWidth = SrcWidth - RoundWidth;
|
||||
assert(ExtraWidth < RoundWidth);
|
||||
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
|
||||
"Load size not an integral number of bytes!");
|
||||
EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
|
||||
EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
|
||||
SDValue Lo, Hi, Ch;
|
||||
unsigned IncrementSize;
|
||||
|
||||
if (TLI.isLittleEndian()) {
|
||||
// EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16)
|
||||
// Load the bottom RoundWidth bits.
|
||||
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0),
|
||||
Tmp1, Tmp2,
|
||||
LD->getPointerInfo(), RoundVT, isVolatile,
|
||||
isNonTemporal, Alignment);
|
||||
|
||||
// Load the remaining ExtraWidth bits.
|
||||
IncrementSize = RoundWidth / 8;
|
||||
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
|
||||
DAG.getIntPtrConstant(IncrementSize));
|
||||
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
|
||||
LD->getPointerInfo().getWithOffset(IncrementSize),
|
||||
ExtraVT, isVolatile, isNonTemporal,
|
||||
MinAlign(Alignment, IncrementSize));
|
||||
|
||||
// Build a factor node to remember that this load is independent of
|
||||
// the other one.
|
||||
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
|
||||
Hi.getValue(1));
|
||||
|
||||
// Move the top bits to the right place.
|
||||
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
|
||||
DAG.getConstant(RoundWidth,
|
||||
TLI.getShiftAmountTy(Hi.getValueType())));
|
||||
|
||||
// Join the hi and lo parts.
|
||||
Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
|
||||
} else {
|
||||
// Big endian - avoid unaligned loads.
|
||||
// EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8
|
||||
// Load the top RoundWidth bits.
|
||||
Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Tmp1, Tmp2,
|
||||
LD->getPointerInfo(), RoundVT, isVolatile,
|
||||
isNonTemporal, Alignment);
|
||||
|
||||
// Load the remaining ExtraWidth bits.
|
||||
IncrementSize = RoundWidth / 8;
|
||||
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
|
||||
DAG.getIntPtrConstant(IncrementSize));
|
||||
Lo = DAG.getExtLoad(ISD::ZEXTLOAD,
|
||||
dl, Node->getValueType(0), Tmp1, Tmp2,
|
||||
LD->getPointerInfo().getWithOffset(IncrementSize),
|
||||
ExtraVT, isVolatile, isNonTemporal,
|
||||
MinAlign(Alignment, IncrementSize));
|
||||
|
||||
// Build a factor node to remember that this load is independent of
|
||||
// the other one.
|
||||
Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
|
||||
Hi.getValue(1));
|
||||
|
||||
// Move the top bits to the right place.
|
||||
Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi,
|
||||
DAG.getConstant(ExtraWidth,
|
||||
TLI.getShiftAmountTy(Hi.getValueType())));
|
||||
|
||||
// Join the hi and lo parts.
|
||||
Tmp1 = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi);
|
||||
}
|
||||
|
||||
Tmp2 = Ch;
|
||||
} else {
|
||||
switch (TLI.getLoadExtAction(ExtType, SrcVT)) {
|
||||
default: llvm_unreachable("This action is not supported yet!");
|
||||
case TargetLowering::Custom:
|
||||
isCustom = true;
|
||||
// FALLTHROUGH
|
||||
case TargetLowering::Legal:
|
||||
Tmp1 = SDValue(Node, 0);
|
||||
Tmp2 = SDValue(Node, 1);
|
||||
|
||||
if (isCustom) {
|
||||
Tmp3 = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Tmp3.getNode()) {
|
||||
Tmp1 = Tmp3;
|
||||
Tmp2 = Tmp3.getValue(1);
|
||||
}
|
||||
} else {
|
||||
// If this is an unaligned load and the target doesn't support it,
|
||||
// expand it.
|
||||
if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
|
||||
Type *Ty =
|
||||
LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
|
||||
unsigned ABIAlignment =
|
||||
TLI.getTargetData()->getABITypeAlignment(Ty);
|
||||
if (LD->getAlignment() < ABIAlignment){
|
||||
ExpandUnalignedLoad(cast<LoadSDNode>(Node),
|
||||
DAG, TLI, Tmp1, Tmp2);
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
case TargetLowering::Expand:
|
||||
if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) {
|
||||
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2,
|
||||
LD->getPointerInfo(),
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->isInvariant(), LD->getAlignment());
|
||||
unsigned ExtendOp;
|
||||
switch (ExtType) {
|
||||
case ISD::EXTLOAD:
|
||||
ExtendOp = (SrcVT.isFloatingPoint() ?
|
||||
ISD::FP_EXTEND : ISD::ANY_EXTEND);
|
||||
break;
|
||||
case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break;
|
||||
case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break;
|
||||
default: llvm_unreachable("Unexpected extend load type!");
|
||||
}
|
||||
Tmp1 = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load);
|
||||
Tmp2 = Load.getValue(1);
|
||||
break;
|
||||
}
|
||||
|
||||
assert(!SrcVT.isVector() &&
|
||||
"Vector Loads are handled in LegalizeVectorOps");
|
||||
|
||||
// FIXME: This does not work for vectors on most targets. Sign- and
|
||||
// zero-extend operations are currently folded into extending loads,
|
||||
// whether they are legal or not, and then we end up here without any
|
||||
// support for legalizing them.
|
||||
assert(ExtType != ISD::EXTLOAD &&
|
||||
"EXTLOAD should always be supported!");
|
||||
// Turn the unsupported load into an EXTLOAD followed by an explicit
|
||||
// zero/sign extend inreg.
|
||||
SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0),
|
||||
Tmp1, Tmp2, LD->getPointerInfo(), SrcVT,
|
||||
LD->isVolatile(), LD->isNonTemporal(),
|
||||
LD->getAlignment());
|
||||
SDValue ValRes;
|
||||
if (ExtType == ISD::SEXTLOAD)
|
||||
ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl,
|
||||
Result.getValueType(),
|
||||
Result, DAG.getValueType(SrcVT));
|
||||
else
|
||||
ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType());
|
||||
Tmp1 = ValRes;
|
||||
Tmp2 = Result.getValue(1);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
// Since loads produce two values, make sure to remember that we legalized
|
||||
// both of them.
|
||||
if (Tmp2.getNode() != Node) {
|
||||
assert(Tmp1.getNode() != Node && "Load must be completely replaced");
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp1);
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Tmp2);
|
||||
ReplacedNode(Node);
|
||||
}
|
||||
break;
|
||||
return LegalizeLoadOps(Node);
|
||||
}
|
||||
case ISD::STORE: {
|
||||
StoreSDNode *ST = cast<StoreSDNode>(Node);
|
||||
Tmp1 = ST->getChain();
|
||||
Tmp2 = ST->getBasePtr();
|
||||
unsigned Alignment = ST->getAlignment();
|
||||
bool isVolatile = ST->isVolatile();
|
||||
bool isNonTemporal = ST->isNonTemporal();
|
||||
|
||||
if (!ST->isTruncatingStore()) {
|
||||
if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) {
|
||||
ReplaceNode(ST, OptStore);
|
||||
break;
|
||||
}
|
||||
|
||||
{
|
||||
Tmp3 = ST->getValue();
|
||||
EVT VT = Tmp3.getValueType();
|
||||
switch (TLI.getOperationAction(ISD::STORE, VT)) {
|
||||
default: llvm_unreachable("This action is not supported yet!");
|
||||
case TargetLowering::Legal:
|
||||
// If this is an unaligned store and the target doesn't support it,
|
||||
// expand it.
|
||||
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
|
||||
Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
|
||||
unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
|
||||
if (ST->getAlignment() < ABIAlignment)
|
||||
ExpandUnalignedStore(cast<StoreSDNode>(Node),
|
||||
DAG, TLI, this);
|
||||
}
|
||||
break;
|
||||
case TargetLowering::Custom:
|
||||
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Tmp1.getNode())
|
||||
ReplaceNode(SDValue(Node, 0), Tmp1);
|
||||
break;
|
||||
case TargetLowering::Promote: {
|
||||
assert(VT.isVector() && "Unknown legal promote case!");
|
||||
Tmp3 = DAG.getNode(ISD::BITCAST, dl,
|
||||
TLI.getTypeToPromoteTo(ISD::STORE, VT), Tmp3);
|
||||
SDValue Result =
|
||||
DAG.getStore(Tmp1, dl, Tmp3, Tmp2,
|
||||
ST->getPointerInfo(), isVolatile,
|
||||
isNonTemporal, Alignment);
|
||||
ReplaceNode(SDValue(Node, 0), Result);
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
Tmp3 = ST->getValue();
|
||||
|
||||
EVT StVT = ST->getMemoryVT();
|
||||
unsigned StWidth = StVT.getSizeInBits();
|
||||
|
||||
if (StWidth != StVT.getStoreSizeInBits()) {
|
||||
// Promote to a byte-sized store with upper bits zero if not
|
||||
// storing an integral number of bytes. For example, promote
|
||||
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
|
||||
EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
|
||||
StVT.getStoreSizeInBits());
|
||||
Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
|
||||
SDValue Result =
|
||||
DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
|
||||
NVT, isVolatile, isNonTemporal, Alignment);
|
||||
ReplaceNode(SDValue(Node, 0), Result);
|
||||
} else if (StWidth & (StWidth - 1)) {
|
||||
// If not storing a power-of-2 number of bits, expand as two stores.
|
||||
assert(!StVT.isVector() && "Unsupported truncstore!");
|
||||
unsigned RoundWidth = 1 << Log2_32(StWidth);
|
||||
assert(RoundWidth < StWidth);
|
||||
unsigned ExtraWidth = StWidth - RoundWidth;
|
||||
assert(ExtraWidth < RoundWidth);
|
||||
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
|
||||
"Store size not an integral number of bytes!");
|
||||
EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth);
|
||||
EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth);
|
||||
SDValue Lo, Hi;
|
||||
unsigned IncrementSize;
|
||||
|
||||
if (TLI.isLittleEndian()) {
|
||||
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16)
|
||||
// Store the bottom RoundWidth bits.
|
||||
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
|
||||
RoundVT,
|
||||
isVolatile, isNonTemporal, Alignment);
|
||||
|
||||
// Store the remaining ExtraWidth bits.
|
||||
IncrementSize = RoundWidth / 8;
|
||||
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
|
||||
DAG.getIntPtrConstant(IncrementSize));
|
||||
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
|
||||
DAG.getConstant(RoundWidth,
|
||||
TLI.getShiftAmountTy(Tmp3.getValueType())));
|
||||
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2,
|
||||
ST->getPointerInfo().getWithOffset(IncrementSize),
|
||||
ExtraVT, isVolatile, isNonTemporal,
|
||||
MinAlign(Alignment, IncrementSize));
|
||||
} else {
|
||||
// Big endian - avoid unaligned stores.
|
||||
// TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X
|
||||
// Store the top RoundWidth bits.
|
||||
Hi = DAG.getNode(ISD::SRL, dl, Tmp3.getValueType(), Tmp3,
|
||||
DAG.getConstant(ExtraWidth,
|
||||
TLI.getShiftAmountTy(Tmp3.getValueType())));
|
||||
Hi = DAG.getTruncStore(Tmp1, dl, Hi, Tmp2, ST->getPointerInfo(),
|
||||
RoundVT, isVolatile, isNonTemporal, Alignment);
|
||||
|
||||
// Store the remaining ExtraWidth bits.
|
||||
IncrementSize = RoundWidth / 8;
|
||||
Tmp2 = DAG.getNode(ISD::ADD, dl, Tmp2.getValueType(), Tmp2,
|
||||
DAG.getIntPtrConstant(IncrementSize));
|
||||
Lo = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
|
||||
ST->getPointerInfo().getWithOffset(IncrementSize),
|
||||
ExtraVT, isVolatile, isNonTemporal,
|
||||
MinAlign(Alignment, IncrementSize));
|
||||
}
|
||||
|
||||
// The order of the stores doesn't matter.
|
||||
SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
|
||||
ReplaceNode(SDValue(Node, 0), Result);
|
||||
} else {
|
||||
switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) {
|
||||
default: llvm_unreachable("This action is not supported yet!");
|
||||
case TargetLowering::Legal:
|
||||
// If this is an unaligned store and the target doesn't support it,
|
||||
// expand it.
|
||||
if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
|
||||
Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext());
|
||||
unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty);
|
||||
if (ST->getAlignment() < ABIAlignment)
|
||||
ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this);
|
||||
}
|
||||
break;
|
||||
case TargetLowering::Custom:
|
||||
Tmp1 = TLI.LowerOperation(SDValue(Node, 0), DAG);
|
||||
if (Tmp1.getNode())
|
||||
ReplaceNode(SDValue(Node, 0), Tmp1);
|
||||
break;
|
||||
case TargetLowering::Expand:
|
||||
assert(!StVT.isVector() &&
|
||||
"Vector Stores are handled in LegalizeVectorOps");
|
||||
|
||||
// TRUNCSTORE:i16 i32 -> STORE i16
|
||||
assert(TLI.isTypeLegal(StVT) && "Do not know how to expand this store!");
|
||||
Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
|
||||
SDValue Result =
|
||||
DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
|
||||
isVolatile, isNonTemporal, Alignment);
|
||||
ReplaceNode(SDValue(Node, 0), Result);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
return LegalizeStoreOps(Node);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue