forked from OSchip/llvm-project
AMDGPU: Shrink insts to fold immediates
This needs to be done in the SSA fold operands pass to be effective, so there is a bit of overlap with SIShrinkInstructions but I don't think this is practically avoidable. llvm-svn: 340859
This commit is contained in:
Matt Arsenault
parent
ec71e018d6
commit
de6c421cc8
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@ -35,13 +35,16 @@ struct FoldCandidate {
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uint64_t ImmToFold;
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int FrameIndexToFold;
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};
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int ShrinkOpcode;
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unsigned char UseOpNo;
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MachineOperand::MachineOperandType Kind;
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bool Commuted;
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FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp,
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bool Commuted_ = false) :
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UseMI(MI), OpToFold(nullptr), UseOpNo(OpNo), Kind(FoldOp->getType()),
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bool Commuted_ = false,
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int ShrinkOp = -1) :
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UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
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Kind(FoldOp->getType()),
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Commuted(Commuted_) {
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if (FoldOp->isImm()) {
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ImmToFold = FoldOp->getImm();
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@ -68,6 +71,14 @@ struct FoldCandidate {
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bool isCommuted() const {
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return Commuted;
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}
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bool needsShrink() const {
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return ShrinkOpcode != -1;
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}
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int getShrinkOpcode() const {
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return ShrinkOpcode;
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}
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};
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class SIFoldOperands : public MachineFunctionPass {
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@ -154,6 +165,7 @@ FunctionPass *llvm::createSIFoldOperandsPass() {
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}
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static bool updateOperand(FoldCandidate &Fold,
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const SIInstrInfo &TII,
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const TargetRegisterInfo &TRI) {
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MachineInstr *MI = Fold.UseMI;
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MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
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@ -189,10 +201,42 @@ static bool updateOperand(FoldCandidate &Fold,
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Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
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}
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}
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if (Fold.needsShrink()) {
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MachineBasicBlock *MBB = MI->getParent();
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auto Liveness = MBB->computeRegisterLiveness(&TRI, AMDGPU::VCC, MI);
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if (Liveness != MachineBasicBlock::LQR_Dead)
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return false;
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int Op32 = Fold.getShrinkOpcode();
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MachineOperand &Dst0 = MI->getOperand(0);
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MachineOperand &Dst1 = MI->getOperand(1);
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assert(Dst0.isDef() && Dst1.isDef());
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MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
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const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
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unsigned NewReg0 = MRI.createVirtualRegister(Dst0RC);
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const TargetRegisterClass *Dst1RC = MRI.getRegClass(Dst1.getReg());
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unsigned NewReg1 = MRI.createVirtualRegister(Dst1RC);
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MachineInstr *Inst32 = TII.buildShrunkInst(*MI, Op32);
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// Keep the old instruction around to avoid breaking iterators, but
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// replace the outputs with dummy registers.
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Dst0.setReg(NewReg0);
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Dst1.setReg(NewReg1);
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if (Fold.isCommuted())
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TII.commuteInstruction(*Inst32, false);
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return true;
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}
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Old.ChangeToImmediate(Fold.ImmToFold);
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return true;
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}
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assert(!Fold.needsShrink() && "not handled");
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if (Fold.isFI()) {
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Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
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return true;
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@ -261,6 +305,8 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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if (isUseMIInFoldList(FoldList, MI))
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return false;
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unsigned CommuteOpNo = OpNo;
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// Operand is not legal, so try to commute the instruction to
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// see if this makes it possible to fold.
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unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
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@ -269,11 +315,12 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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if (CanCommute) {
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if (CommuteIdx0 == OpNo)
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OpNo = CommuteIdx1;
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CommuteOpNo = CommuteIdx1;
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else if (CommuteIdx1 == OpNo)
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OpNo = CommuteIdx0;
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CommuteOpNo = CommuteIdx0;
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}
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// One of operands might be an Imm operand, and OpNo may refer to it after
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// the call of commuteInstruction() below. Such situations are avoided
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// here explicitly as OpNo must be a register operand to be a candidate
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@ -286,12 +333,39 @@ static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
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!TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
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return false;
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if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
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if (!TII->isOperandLegal(*MI, CommuteOpNo, OpToFold)) {
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if ((Opc == AMDGPU::V_ADD_I32_e64 ||
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Opc == AMDGPU::V_SUB_I32_e64 ||
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Opc == AMDGPU::V_SUBREV_I32_e64) && // FIXME
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OpToFold->isImm()) {
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MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
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// Verify the other operand is a VGPR, otherwise we would violate the
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// constant bus restriction.
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unsigned OtherIdx = CommuteOpNo == CommuteIdx0 ? CommuteIdx1 : CommuteIdx0;
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MachineOperand &OtherOp = MI->getOperand(OtherIdx);
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if (!OtherOp.isReg() ||
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!TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
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return false;
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const MachineOperand &SDst = MI->getOperand(1);
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assert(SDst.isDef());
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// TODO: Handle cases with a used carry.
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if (!MRI.use_nodbg_empty(SDst.getReg()))
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return false;
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int Op32 = AMDGPU::getVOPe32(Opc);
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FoldList.push_back(FoldCandidate(MI, CommuteOpNo, OpToFold, true,
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Op32));
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return true;
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}
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TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1);
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return false;
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}
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FoldList.push_back(FoldCandidate(MI, OpNo, OpToFold, true));
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FoldList.push_back(FoldCandidate(MI, CommuteOpNo, OpToFold, true));
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return true;
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}
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@ -757,7 +831,7 @@ void SIFoldOperands::foldInstOperand(MachineInstr &MI,
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Copy->addImplicitDefUseOperands(*MF);
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for (FoldCandidate &Fold : FoldList) {
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if (updateOperand(Fold, *TRI)) {
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if (updateOperand(Fold, *TII, *TRI)) {
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// Clear kill flags.
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if (Fold.isReg()) {
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assert(Fold.OpToFold && Fold.OpToFold->isReg());
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@ -2572,7 +2572,60 @@ bool SIInstrInfo::canShrink(const MachineInstr &MI,
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// Check output modifiers
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return !hasModifiersSet(MI, AMDGPU::OpName::omod) &&
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!hasModifiersSet(MI, AMDGPU::OpName::clamp);
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}
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// Set VCC operand with all flags from \p Orig, except for setting it as
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// implicit.
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static void copyFlagsToImplicitVCC(MachineInstr &MI,
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const MachineOperand &Orig) {
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for (MachineOperand &Use : MI.implicit_operands()) {
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if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
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Use.setIsUndef(Orig.isUndef());
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Use.setIsKill(Orig.isKill());
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return;
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}
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}
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}
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MachineInstr *SIInstrInfo::buildShrunkInst(MachineInstr &MI,
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unsigned Op32) const {
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MachineBasicBlock *MBB = MI.getParent();;
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MachineInstrBuilder Inst32 =
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BuildMI(*MBB, MI, MI.getDebugLoc(), get(Op32));
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// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
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// For VOPC instructions, this is replaced by an implicit def of vcc.
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int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
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if (Op32DstIdx != -1) {
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// dst
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Inst32.add(MI.getOperand(0));
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} else {
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assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
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"Unexpected case");
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}
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Inst32.add(*getNamedOperand(MI, AMDGPU::OpName::src0));
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const MachineOperand *Src1 = getNamedOperand(MI, AMDGPU::OpName::src1);
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if (Src1)
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Inst32.add(*Src1);
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const MachineOperand *Src2 = getNamedOperand(MI, AMDGPU::OpName::src2);
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if (Src2) {
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int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
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if (Op32Src2Idx != -1) {
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Inst32.add(*Src2);
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} else {
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// In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
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// replaced with an implicit read of vcc. This was already added
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// during the initial BuildMI, so find it to preserve the flags.
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copyFlagsToImplicitVCC(*Inst32, *Src2);
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}
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}
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return Inst32;
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}
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bool SIInstrInfo::usesConstantBus(const MachineRegisterInfo &MRI,
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@ -694,6 +694,9 @@ public:
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bool canShrink(const MachineInstr &MI,
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const MachineRegisterInfo &MRI) const;
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MachineInstr *buildShrunkInst(MachineInstr &MI,
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unsigned NewOpcode) const;
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bool verifyInstruction(const MachineInstr &MI,
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StringRef &ErrInfo) const override;
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@ -120,19 +120,6 @@ static bool foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
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return false;
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}
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// Copy MachineOperand with all flags except setting it as implicit.
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static void copyFlagsToImplicitVCC(MachineInstr &MI,
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const MachineOperand &Orig) {
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for (MachineOperand &Use : MI.implicit_operands()) {
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if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
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Use.setIsUndef(Orig.isUndef());
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Use.setIsKill(Orig.isKill());
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return;
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}
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}
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}
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static bool isKImmOperand(const SIInstrInfo *TII, const MachineOperand &Src) {
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return isInt<16>(Src.getImm()) &&
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!TII->isInlineConstant(*Src.getParent(),
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@ -434,40 +421,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
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// We can shrink this instruction
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LLVM_DEBUG(dbgs() << "Shrinking " << MI);
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MachineInstrBuilder Inst32 =
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BuildMI(MBB, I, MI.getDebugLoc(), TII->get(Op32));
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// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
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// For VOPC instructions, this is replaced by an implicit def of vcc.
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int Op32DstIdx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst);
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if (Op32DstIdx != -1) {
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// dst
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Inst32.add(MI.getOperand(0));
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} else {
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assert(MI.getOperand(0).getReg() == AMDGPU::VCC &&
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"Unexpected case");
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}
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Inst32.add(*TII->getNamedOperand(MI, AMDGPU::OpName::src0));
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const MachineOperand *Src1 =
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TII->getNamedOperand(MI, AMDGPU::OpName::src1);
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if (Src1)
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Inst32.add(*Src1);
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if (Src2) {
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int Op32Src2Idx = AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::src2);
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if (Op32Src2Idx != -1) {
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Inst32.add(*Src2);
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} else {
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// In the case of V_CNDMASK_B32_e32, the explicit operand src2 is
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// replaced with an implicit read of vcc. This was already added
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// during the initial BuildMI, so find it to preserve the flags.
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copyFlagsToImplicitVCC(*Inst32, *Src2);
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}
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}
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MachineInstr *Inst32 = TII->buildShrunkInst(MI, Op32);
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++NumInstructionsShrunk;
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// Copy extra operands not present in the instruction definition.
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@ -0,0 +1,79 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
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---
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# Uses a carry out in an instruction that can't be shrunk.
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_other_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_other_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[DEF]], [[S_MOV_B32_]], implicit $exec
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; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_1]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
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S_ENDPGM implicit %5
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...
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---
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# TODO: Is it OK to leave the broken use around on the DBG_VALUE?
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_dbg_only_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_dbg_only_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
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; GCN: DBG_VALUE debug-use %5:sreg_64_xexec, debug-use $noreg
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; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
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DBG_VALUE debug-use %5, debug-use $noreg
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S_ENDPGM implicit %4
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...
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---
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# Uses carry out in a normal pattern
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[DEF1:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 [[DEF]], [[S_MOV_B32_]], implicit $exec
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; GCN: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 [[DEF1]], [[DEF2]], [[V_ADD_I32_e64_1]], implicit $exec
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; GCN: S_ENDPGM implicit [[V_ADDC_U32_e64_]]
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%0:sreg_32_xm0 = S_MOV_B32 12345
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%1:vgpr_32 = IMPLICIT_DEF
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%2:vgpr_32 = IMPLICIT_DEF
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%3:vgpr_32 = IMPLICIT_DEF
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%4:vgpr_32, %5:sreg_64_xexec = V_ADD_I32_e64 %0, %1, implicit $exec
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%6:vgpr_32, %7:sreg_64_xexec = V_ADDC_U32_e64 %2, %3, %5, implicit $exec
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S_ENDPGM implicit %6
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...
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@ -0,0 +1,347 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -run-pass si-fold-operands,dead-mi-elimination %s -o - | FileCheck -check-prefix=GCN %s
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---
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name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
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tracksRegLiveness: true
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body: |
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bb.0:
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; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_no_carry_out_use
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; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
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; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_add_i32_e64_no_carry_out_use
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
|
||||
%0:vgpr_32 = IMPLICIT_DEF
|
||||
%1:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_carry_out_use
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e32_]]
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# This does not shrink because it would violate the constant bus
|
||||
# restriction. to have an SGPR input and an immediate, so a copy would
|
||||
# be required.
|
||||
|
||||
name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_vector_imm_sgpr_v_add_i32_e64_no_carry_out_use
|
||||
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[DEF]], [[V_MOV_B32_e32_]], implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]]
|
||||
%0:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
%1:sreg_32_xm0 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_sgpr_vector_imm_v_add_i32_e64_no_carry_out_use
|
||||
; GCN: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
|
||||
; GCN: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[V_MOV_B32_e32_]], [[DEF]], implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]]
|
||||
%0:sreg_32_xm0 = IMPLICIT_DEF
|
||||
%1:vgpr_32 = V_MOV_B32_e32 12345, implicit $exec
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_live_vcc_use
|
||||
; GCN: $vcc = S_MOV_B64 -1
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc
|
||||
$vcc = S_MOV_B64 -1
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2, implicit $vcc
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_use
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: $vcc = S_MOV_B64 -1
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: bb.1:
|
||||
; GCN: liveins: $vcc
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
$vcc = S_MOV_B64 -1
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
|
||||
bb.1:
|
||||
liveins: $vcc
|
||||
S_ENDPGM implicit %2, implicit $vcc
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_liveout_vcc_lo_use
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: bb.1:
|
||||
; GCN: liveins: $vcc_lo
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
$vcc = S_MOV_B64 -1
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
|
||||
bb.1:
|
||||
liveins: $vcc_lo
|
||||
S_ENDPGM implicit %2, implicit $vcc_lo
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
# This is not OK to clobber because vcc_lo has a livein use.
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: $vcc = S_MOV_B64 -1
|
||||
; GCN: bb.1:
|
||||
; GCN: liveins: $vcc
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_lo
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
$vcc = S_MOV_B64 -1
|
||||
|
||||
bb.1:
|
||||
liveins: $vcc
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2, implicit $vcc_lo
|
||||
|
||||
...
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_livein_vcc_hi
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: $vcc_hi = S_MOV_B32 -1
|
||||
; GCN: bb.1:
|
||||
; GCN: successors: %bb.2(0x80000000)
|
||||
; GCN: liveins: $vcc_hi
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: bb.2:
|
||||
; GCN: liveins: $vcc_hi
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]], implicit $vcc_hi
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
$vcc_hi = S_MOV_B32 -1
|
||||
|
||||
bb.1:
|
||||
liveins: $vcc_hi
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
|
||||
bb.2:
|
||||
liveins: $vcc_hi
|
||||
|
||||
S_ENDPGM implicit %2, implicit $vcc_hi
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_sub_i32_e64_no_carry_out_use
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_sub_i32_e64_no_carry_out_use
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
|
||||
%0:vgpr_32 = IMPLICIT_DEF
|
||||
%1:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%2:vgpr_32, %3:sreg_64 = V_SUB_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_subrev_i32_e64_no_carry_out_use
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_SUB_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUB_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_SUB_I32_e32_]]
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
; GCN-LABEL: name: shrink_vgpr_scalar_imm_v_subrev_i32_e64_no_carry_out_use
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[V_SUBREV_I32_e32_:%[0-9]+]]:vgpr_32 = V_SUBREV_I32_e32 [[S_MOV_B32_]], [[DEF]], implicit-def $vcc, implicit $exec
|
||||
; GCN: S_ENDPGM implicit [[V_SUBREV_I32_e32_]]
|
||||
%0:vgpr_32 = IMPLICIT_DEF
|
||||
%1:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%2:vgpr_32, %3:sreg_64 = V_SUBREV_I32_e64 %0, %1, implicit $exec
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
# We know this is OK because vcc isn't live out of the block, even
|
||||
# though it had a defined value
|
||||
|
||||
name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_dead_no_liveout
|
||||
tracksRegLiveness: true
|
||||
|
||||
body: |
|
||||
; GCN-LABEL: name: shrink_scalar_imm_vgpr_v_add_i32_e64_known_dead_no_liveout
|
||||
; GCN: bb.0:
|
||||
; GCN: successors: %bb.1(0x80000000)
|
||||
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 12345
|
||||
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
|
||||
; GCN: [[V_ADD_I32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_I32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_I32_e64 [[S_MOV_B32_]], [[DEF]], implicit $exec
|
||||
; GCN: bb.1:
|
||||
; GCN: S_ENDPGM implicit [[V_ADD_I32_e64_]]
|
||||
bb.0:
|
||||
successors: %bb.1
|
||||
|
||||
$vcc = S_MOV_B64 -1
|
||||
%0:sreg_32_xm0 = S_MOV_B32 12345
|
||||
%1:vgpr_32 = IMPLICIT_DEF
|
||||
%2:vgpr_32, %3:sreg_64 = V_ADD_I32_e64 %0, %1, implicit $exec
|
||||
|
||||
bb.1:
|
||||
S_ENDPGM implicit %2
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue