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[AMDGPU] Add Reset function to GCNHazardRecognizer 

Reset the tracked emitted instructions when starting scheduling on a new
region.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D90347
This commit is contained in:
Austin Kerbow 2020-10-28 14:38:41 -07:00
parent 7d3e9578ca
commit de51867343
4 changed files with 29 additions and 3 deletions
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4
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
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@ -50,6 +50,10 @@ GCNHazardRecognizer::GCNHazardRecognizer(const MachineFunction &MF) :
TSchedModel.init(&ST);
}
void GCNHazardRecognizer::Reset() {
EmittedInstrs.clear();
}
void GCNHazardRecognizer::EmitInstruction(SUnit *SU) {
EmitInstruction(SU->getInstr());
}

1
llvm/lib/Target/AMDGPU/GCNHazardRecognizer.h
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@ -109,6 +109,7 @@ public:
void AdvanceCycle() override;
void RecedeCycle() override;
bool ShouldPreferAnother(SUnit *SU) override;
void Reset() override;
};
} // end namespace llvm

5
llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mov.dpp.ll
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@ -34,12 +34,11 @@ define amdgpu_kernel void @dpp_wait_states(i32 addrspace(1)* %out, i32 %in) {
; VI-LABEL: {{^}}dpp_first_in_bb:
; VI: ; %endif
; PREGFX10-OPT: s_mov_b32
; PREGFX10-OPT: s_mov_b32
; PREGFX10-NOOPT: s_waitcnt
; PREGFX10-NOOPT: v_mov_b32_e32
; VI: v_mov_b32_dpp [[VGPR0:v[0-9]+]], v{{[0-9]+}} quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
; PREGFX10: s_nop 1
; PREGFX10-OPT: s_mov_b32
; PREGFX10-OPT: s_mov_b32
; VI: v_mov_b32_dpp [[VGPR1:v[0-9]+]], [[VGPR0]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0
; PREGFX10: s_nop 1
; VI: v_mov_b32_dpp v{{[0-9]+}}, [[VGPR1]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0

22
llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir Normal file
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@ -0,0 +1,22 @@
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=post-RA-sched -o - %s 2>&1 | FileCheck %s
# REQUIRES: asserts
# CHECK-NOT: Stall in cycle
---
name: hazard_rec_reset
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1
$m0 = S_MOV_B32 0
bb.1:
liveins: $vgpr4
S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
$vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
S_ENDPGM 0
...