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[mips][microMIPS] Add CodeGen support for SUBU16, SUB, SUBU, DSUB and DSUBU instructions 

Differential Revision: http://reviews.llvm.org/D16676

llvm-svn: 267694
This commit is contained in:
Zlatko Buljan 2016-04-27 11:31:44 +00:00
parent 29813620bc
commit de0bbe6d1c
9 changed files with 162 additions and 56 deletions
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6
llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
View File

@ -990,7 +990,9 @@ class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">,
MicroMipsR6Inst16;
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
MMR6Arch<"subu16">, MicroMipsR6Inst16;
MMR6Arch<"subu16">, MicroMipsR6Inst16 {
int AddedComplexity = 1;
}
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
MMR6Arch<"xor16">;
@ -1478,3 +1480,5 @@ def : MipsInstAlias<"evp", (EVP_MMR6 ZERO), 0>, ISA_MICROMIPS32R6;
def : MipsPat<(store GPRMM16:$src, addrimm4lsl2:$addr),
(SW16_MMR6 GPRMM16:$src, addrimm4lsl2:$addr)>, ISA_MICROMIPS32R6;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBU_MMR6 GPR32:$lhs, GPR32:$rhs)>, ISA_MICROMIPS32R6;

40
llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td
View File

@ -41,6 +41,8 @@ class DADD_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dadd", 0b100010000>;
class DADDIU_MM64R6_ENC : DADDIU_FM_MMR6<"daddiu">;
class DADDU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"daddu", 0b101010000>;
class LDPC_MMR646_ENC : PCREL18_FM_MMR6<0b110>;
class DSUB_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsub", 0b110010000>;
class DSUBU_MM64R6_ENC : POOL32S_ARITH_FM_MMR6<"dsubu", 0b111010000>;
//===----------------------------------------------------------------------===//
//
@ -124,6 +126,24 @@ class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd,
IsAsCheapAsAMove;
class DADDU_MM64R6_DESC : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>;
class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO,
InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag>
: MipsR6Inst {
dag OutOperandList = (outs RO:$rd);
dag InOperandList = (ins RO:$rs, RO:$rt);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt");
list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rs, RO:$rt))];
InstrItinClass Itinerary = Itin;
Format Form = FrmR;
string BaseOpcode = instr_asm;
let isCommutable = 0;
let isReMaterializable = 1;
let TwoOperandAliasConstraint = "$rd = $rs";
}
class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>;
class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>;
class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>;
//===----------------------------------------------------------------------===//
@ -178,6 +198,10 @@ let DecoderNamespace = "MicroMipsR6" in {
ISA_MICROMIPS64R6;
def LDPC_MM64R6 : R6MMR6Rel, LDPC_MMR646_ENC, LDPC_MM64R6_DESC,
ISA_MICROMIPS64R6;
def DSUB_MM64R6 : StdMMR6Rel, DSUB_MM64R6_DESC, DSUB_MM64R6_ENC,
ISA_MICROMIPS64R6;
def DSUBU_MM64R6 : StdMMR6Rel, DSUBU_MM64R6_DESC, DSUBU_MM64R6_ENC,
ISA_MICROMIPS64R6;
}
//===----------------------------------------------------------------------===//
@ -222,6 +246,10 @@ def : WrapperPat<tblockaddress, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
def : WrapperPat<tjumptable, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
def : WrapperPat<tglobaltlsaddr, DADDIU_MM64R6, GPR64>, ISA_MICROMIPS64R6;
// Carry pattern
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
(DSUBU_MM64R6 GPR64:$lhs, GPR64:$rhs)>, ISA_MICROMIPS64R6;
//===----------------------------------------------------------------------===//
//
// Instruction aliases
@ -253,3 +281,15 @@ def : MipsInstAlias<"dsubu $rs, $imm",
GPR64Opnd:$rs,
InvertedImOperand64:$imm),
0>, ISA_MICROMIPS64R6;
def : MipsInstAlias<"dneg $rt, $rs",
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dneg $rt",
(DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MICROMIPS64R6;
def : MipsInstAlias<"dnegu $rt",
(DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
ISA_MICROMIPS64R6;

2
llvm/lib/Target/Mips/MicroMipsInstrInfo.td
View File

@ -996,6 +996,8 @@ def : MipsPat<(load addrimm4lsl2:$addr),
(LW16_MM addrimm4lsl2:$addr)>;
def : MipsPat<(load addr:$addr),
(LW_MM addr:$addr)>;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
//===----------------------------------------------------------------------===//
// MicroMips instruction aliases

32
llvm/lib/Target/Mips/Mips64InstrInfo.td
View File

@ -120,11 +120,11 @@ let AdditionalPredicates = [NotInMicroMips] in {
ADD_FM<0, 0x2c>, ISA_MIPS3;
def DADDu : StdMMR6Rel, ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
ADD_FM<0, 0x2d>, ISA_MIPS3;
def DSUBu : StdMMR6Rel, ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
ISA_MIPS3;
def DSUB : StdMMR6Rel, ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
ISA_MIPS3;
}
def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>, ADD_FM<0, 0x2f>,
ISA_MIPS3;
def DSUB : ArithLogicR<"dsub", GPR64Opnd, 0, II_DSUB>, ADD_FM<0, 0x2e>,
ISA_MIPS3;
let isCodeGenOnly = 1 in {
def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
@ -554,9 +554,9 @@ def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
// Carry pattern
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(subc GPR64:$lhs, GPR64:$rhs),
(DSUBu GPR64:$lhs, GPR64:$rhs)>;
def : MipsPat<(addc GPR64:$lhs, GPR64:$rhs),
(DADDu GPR64:$lhs, GPR64:$rhs)>, ASE_NOT_DSP;
def : MipsPat<(addc GPR64:$lhs, immSExt16:$imm),
@ -611,15 +611,17 @@ let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dsll $rd, $rt, $rs",
(DSLLV GPR64Opnd:$rd, GPR64Opnd:$rt, GPR32Opnd:$rs), 0>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt, $rs",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsInstAlias<"dneg $rt, $rs",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
def : MipsInstAlias<"dneg $rt",
(DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>,
ISA_MIPS3;
def : MipsInstAlias<"dnegu $rt, $rs",
(DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>,
ISA_MIPS3;
}
def : MipsInstAlias<"dsubi $rs, $rt, $imm",
(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt,
InvertedImOperand64:$imm),

10
llvm/lib/Target/Mips/MipsInstrInfo.td
View File

@ -1668,14 +1668,14 @@ let AdditionalPredicates = [NotInMicroMips] in {
/// Arithmetic Instructions (3-Operand, R-Type)
def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
ADD_FM<0, 0x21>;
def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
ADD_FM<0, 0x23>;
}
let Defs = [HI0, LO0] in
def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
let AdditionalPredicates = [NotInMicroMips] in {
@ -2404,8 +2404,10 @@ def : MipsPat<(i32 imm:$imm),
(ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
// Carry MipsPatterns
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu GPR32:$lhs, GPR32:$rhs)>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu GPR32:$lhs, GPR32:$rhs)>;
}
def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
(ADDu GPR32:$lhs, GPR32:$rhs)>, ASE_NOT_DSP;
def : MipsPat<(addc GPR32:$src, immSExt16:$imm),

112
llvm/test/CodeGen/Mips/llvm-ir/sub.ll
View File

@ -1,37 +1,53 @@
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32
; RUN: -check-prefix=R2-R6 -check-prefix=GP32 -check-prefix=GP32-NOT-MM \
; RUN: -check-prefix=NOT-MM
; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefix=GP32-MM -check-prefix=GP32 -check-prefix=MM
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64
; RUN: -check-prefix=NOT-R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64
; RUN: -check-prefix=R2-R6 -check-prefix=GP64 -check-prefix=NOT-MM
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
; RUN: -check-prefix=GP64 -check-prefix=MM
define signext i1 @sub_i1(i1 signext %a, i1 signext %b) {
entry:
; ALL-LABEL: sub_i1:
; ALL: subu $[[T0:[0-9]+]], $4, $5
; ALL: sll $[[T0]], $[[T0]], 31
; ALL: sra $2, $[[T0]], 31
; NOT-MM: subu $[[T0:[0-9]+]], $4, $5
; NOT-MM: sll $[[T0]], $[[T0]], 31
; NOT-MM: sra $2, $[[T0]], 31
; MM: subu16 $[[T0:[0-9]+]], $4, $5
; MM: sll $[[T1:[0-9]+]], $[[T0]], 31
; MM: sra $[[T0]], $[[T1]], 31
%r = sub i1 %a, %b
ret i1 %r
@ -48,6 +64,9 @@ entry:
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seb $2, $[[T0:[0-9]+]]
; MM: subu16 $[[T0:[0-9]+]], $4, $5
; MM: seb $[[T0]], $[[T0]]
%r = sub i8 %a, %b
ret i8 %r
}
@ -63,6 +82,9 @@ entry:
; R2-R6: subu $[[T0:[0-9]+]], $4, $5
; R2-R6: seh $2, $[[T0:[0-9]+]]
; MM: subu16 $[[T0:[0-9]+]], $4, $5
; MM: seh $[[T0]], $[[T0]]
%r = sub i16 %a, %b
ret i16 %r
}
@ -71,7 +93,9 @@ define signext i32 @sub_i32(i32 signext %a, i32 signext %b) {
entry:
; ALL-LABEL: sub_i32:
; ALL: subu $2, $4, $5
; NOT-MM: subu $2, $4, $5
; MM: subu16 $2, $4, $5
%r = sub i32 %a, %b
ret i32 %r
@ -96,26 +120,42 @@ define signext i128 @sub_i128(i128 signext %a, i128 signext %b) {
entry:
; ALL-LABEL: sub_i128:
; GP32: lw $[[T0:[0-9]+]], 20($sp)
; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]]
; GP32: lw $[[T2:[0-9]+]], 16($sp)
; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; GP32: lw $[[T4:[0-9]+]], 24($sp)
; GP32: lw $[[T5:[0-9]+]], 28($sp)
; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]]
; GP32: subu $2, $4, $[[T3]]
; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]]
; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
; GP32: subu $3, $5, $[[T9]]
; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]]
; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
; GP32: subu $4, $6, $[[T11]]
; GP32: move $5, $[[T6]]
; GP32-NOT-MM: lw $[[T0:[0-9]+]], 20($sp)
; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
; GP32-NOT-MM: lw $[[T2:[0-9]+]], 16($sp)
; GP32-NOT-MM: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]]
; GP32-NOT-MM: lw $[[T4:[0-9]+]], 24($sp)
; GP32-NOT-MM: lw $[[T5:[0-9]+]], 28($sp)
; GP32-NOT-MM: subu $[[T6:[0-9]+]], $7, $[[T5]]
; GP32-NOT-MM: subu $2, $4, $[[T3]]
; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
; GP32-NOT-MM: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]]
; GP32-NOT-MM: subu $3, $5, $[[T9]]
; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
; GP32-NOT-MM: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]]
; GP32-NOT-MM: subu $4, $6, $[[T11]]
; GP32-NOT-MM: move $5, $[[T6]]
; GP64: dsubu $3, $5, $7
; GP64: sltu $[[T0:[0-9]+]], $5, $7
; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
; GP64: dsubu $2, $4, $[[T1]]
; GP32-MM: lw $[[T0:[0-9]+]], 20($sp)
; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
; GP32-MM: lw $[[T3:[0-9]+]], 16($sp)
; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]]
; GP32-MM: lw $[[T4:[0-9]+]], 28($sp)
; GP32-MM: subu $[[T1]], $7, $[[T4]]
; GP32-MM: subu $[[T3]], $[[T5:[0-9]+]], $[[T3]]
; GP32-MM: lw $[[T5]], 24($sp)
; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]]
; GP32-MM: subu $[[T0]], $5, $[[T0]]
; GP32-MM: sltu $[[T2]], $7, $[[T4]]
; GP32-MM: addu $[[T5]], $[[T2]], $[[T5]]
; GP32-MM: subu $[[T5]], $6, $[[T5]]
; GP32-MM: move $[[T2]], $[[T1]]
; GP64: dsubu $3, $5, $7
; GP64: sltu $[[T0:[0-9]+]], $5, $7
; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6
; GP64: dsubu $2, $4, $[[T1]]
%r = sub i128 %a, %b
ret i128 %r

6
llvm/test/MC/Disassembler/Mips/micromips64r6/valid.txt
View File

@ -232,3 +232,9 @@
0x00 0x65 0x10 0x90 # CHECK: srav $2, $3, $5
0x00 0x83 0x38 0x40 # CHECK: srl $4, $3, 7
0x00 0x65 0x10 0x50 # CHECK: srlv $2, $3, $5
0x58 0x62 0x09 0x90 # CHECK: dsub $1, $2, $3
0x59 0xe7 0x19 0xd0 # CHECK: dsubu $3, $7, $15
0x59 0xe0 0x39 0x90 # CHECK: dneg $7, $15
0x59 0x40 0x51 0x90 # CHECK: dneg $10, $10
0x59 0x60 0x09 0xd0 # CHECK: dnegu $1, $11
0x58 0xa0 0x29 0xd0 # CHECK: dnegu $5, $5

4
llvm/test/MC/Mips/micromips64r6/invalid.s
View File

@ -176,3 +176,7 @@
sra $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
srl $3, -1 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
srl $3, 32 # CHECK: :[[@LINE]]:11: error: expected 5-bit unsigned immediate
dneg $7, 5 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
dneg 4 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
dnegu $1, 3 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
dnegu 7 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

6
llvm/test/MC/Mips/micromips64r6/valid.s
View File

@ -223,5 +223,11 @@ a:
sll $3, 7 # CHECK: sll $3, $3, 7 # encoding: [0x00,0x63,0x38,0x00]
sra $3, 7 # CHECK: sra $3, $3, 7 # encoding: [0x00,0x63,0x38,0x80]
srl $3, 7 # CHECK: srl $3, $3, 7 # encoding: [0x00,0x63,0x38,0x40]
dsub $1, $2, $3 # CHECK: dsub $1, $2, $3 # encoding: [0x58,0x62,0x09,0x90]
dsubu $3, $7, $15 # CHECK: dsubu $3, $7, $15 # encoding: [0x59,0xe7,0x19,0xd0]
dneg $7, $15 # CHECK: dneg $7, $15 # encoding: [0x59,0xe0,0x39,0x90]
dneg $10 # CHECK: dneg $10, $10 # encoding: [0x59,0x40,0x51,0x90]
dnegu $1, $11 # CHECK: dnegu $1, $11 # encoding: [0x59,0x60,0x09,0xd0]
dnegu $5 # CHECK: dnegu $5, $5 # encoding: [0x58,0xa0,0x29,0xd0]
1: