forked from OSchip/llvm-project
mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics.
The latency based scheduling could induce spills in some cases. llvm-svn: 190177
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@ -2469,16 +2469,16 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
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TryCand, Cand, RegExcess))
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return;
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// For loops that are acyclic path limited, aggressively schedule for latency.
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if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
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return;
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// Avoid increasing the max critical pressure in the scheduled region.
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if (DAG->isTrackingPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
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Cand.RPDelta.CriticalMax,
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TryCand, Cand, RegCritical))
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return;
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// For loops that are acyclic path limited, aggressively schedule for latency.
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if (Rem.IsAcyclicLatencyLimited && tryLatency(TryCand, Cand, Zone))
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return;
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// Keep clustered nodes together to encourage downstream peephole
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// optimizations which may reduce resource requirements.
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//
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