forked from OSchip/llvm-project
[LSR] Add test coverage for ICmpZero cases involving urem RHS
For the moment, we're pretty conservative here. My motivating case is the vscale one (as that is idiomatic for scalable vectorized loops on RISCV). There are two obvious approaches to fixing this, and I tried to add reasonable coverage for both even though I'll likely only fix one.
This commit is contained in:
Philip Reames
Philip Reames
parent
6f7347b888
commit
ddd4ed9944
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@ -0,0 +1,188 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-reduce -S | FileCheck %s
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target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
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target triple = "riscv64"
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define void @icmp_zero(i64 %N, ptr %p) {
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; CHECK-LABEL: @icmp_zero(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[VECTOR_BODY]] ], [ [[N:%.*]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -2
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%done = icmp eq i64 %iv.next, %N
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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define void @icmp_zero_urem_nonzero_con(i64 %N, ptr %p) {
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; CHECK-LABEL: @icmp_zero_urem_nonzero_con(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], 16
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[LSR_IV:%.*]] = phi i64 [ [[LSR_IV_NEXT:%.*]], [[VECTOR_BODY]] ], [ [[UREM]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[LSR_IV_NEXT]] = add i64 [[LSR_IV]], -2
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[LSR_IV_NEXT]], 0
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%urem = urem i64 %N, 16
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%done = icmp eq i64 %iv.next, %urem
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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; FIXME: We could handle this case even though we don't know %M. The
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; faulting instruction is already outside the loop!
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define void @icmp_zero_urem_invariant(i64 %N, i64 %M, ptr %p) {
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; CHECK-LABEL: @icmp_zero_urem_invariant(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%urem = urem i64 %N, %M
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%done = icmp eq i64 %iv.next, %urem
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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; Negative test - We can not hoist because we don't know value of %M.
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define void @icmp_zero_urem_nohoist(i64 %N, i64 %M, ptr %p) {
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; CHECK-LABEL: @icmp_zero_urem_nohoist(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%urem = urem i64 %N, %M
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%done = icmp eq i64 %iv.next, %urem
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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define void @icmp_zero_urem_nonzero(i64 %N, i64 %M, ptr %p) {
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; CHECK-LABEL: @icmp_zero_urem_nonzero(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[NONZERO:%.*]] = add nuw i64 [[M:%.*]], 1
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[NONZERO]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%nonzero = add nuw i64 %M, 1
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%urem = urem i64 %N, %nonzero
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%done = icmp eq i64 %iv.next, %urem
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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; FIXME: We can hoist this because vscale is never equal to zero
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define void @icmp_zero_urem_vscale(i64 %N, ptr %p) {
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; CHECK-LABEL: @icmp_zero_urem_vscale(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[N:%.*]], [[VSCALE]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: store i64 0, ptr [[P:%.*]], align 8
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i64 [[IV_NEXT]], [[UREM]]
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; CHECK-NEXT: br i1 [[DONE]], label [[EXIT:%.*]], label [[VECTOR_BODY]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%vscale = call i64 @llvm.vscale.i64()
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%urem = urem i64 %N, %vscale
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br label %vector.body
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vector.body:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %vector.body ]
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store i64 0, ptr %p
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%iv.next = add i64 %iv, 2
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%done = icmp eq i64 %iv.next, %urem
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br i1 %done, label %exit, label %vector.body
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exit:
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ret void
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}
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declare i64 @llvm.vscale.i64()
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@ -0,0 +1,2 @@
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if not 'RISCV' in config.root.targets:
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config.unsupported = True
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