forked from OSchip/llvm-project
[RISCV] Lower the tail pseudoinstruction
This patch lowers the tail pseudoinstruction. This has been modeled after ARM's tail call opt. llvm-svn: 333137
This commit is contained in:
Mandeep Singh Grang
parent
767d92e3fb
commit
ddcb95664e
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@ -85,13 +85,13 @@ MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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return new RISCVMCCodeEmitter(Ctx, MCII);
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}
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// Expand PseudoCALL to AUIPC and JALR with relocation types.
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// We expand PseudoCALL while encoding, meaning AUIPC and JALR won't go through
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// RISCV MC to MC compressed instruction transformation. This is acceptable
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// because AUIPC has no 16-bit form and C_JALR have no immediate operand field.
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// We let linker relaxation deal with it. When linker relaxation enabled,
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// AUIPC and JALR have chance relax to JAL. If C extension is enabled,
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// JAL has chance relax to C_JAL.
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// Expand PseudoCALL and PseudoTAIL to AUIPC and JALR with relocation types.
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// We expand PseudoCALL and PseudoTAIL while encoding, meaning AUIPC and JALR
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// won't go through RISCV MC to MC compressed instruction transformation. This
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// is acceptable because AUIPC has no 16-bit form and C_JALR have no immediate
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// operand field. We let linker relaxation deal with it. When linker
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// relaxation enabled, AUIPC and JALR have chance relax to JAL. If C extension
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// is enabled, JAL has chance relax to C_JAL.
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void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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@ -18,6 +18,7 @@
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#include "RISCVRegisterInfo.h"
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -36,6 +37,8 @@ using namespace llvm;
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#define DEBUG_TYPE "riscv-lower"
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STATISTIC(NumTailCalls, "Number of tail calls");
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RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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const RISCVSubtarget &STI)
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: TargetLowering(TM), Subtarget(STI) {
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@ -1076,6 +1079,88 @@ SDValue RISCVTargetLowering::LowerFormalArguments(
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return Chain;
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}
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/// IsEligibleForTailCallOptimization - Check whether the call is eligible
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/// for tail call optimization.
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/// Note: This is modelled after ARM's IsEligibleForTailCallOptimization.
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bool RISCVTargetLowering::IsEligibleForTailCallOptimization(
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CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
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const SmallVector<CCValAssign, 16> &ArgLocs) const {
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auto &Callee = CLI.Callee;
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auto CalleeCC = CLI.CallConv;
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auto IsVarArg = CLI.IsVarArg;
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auto &Outs = CLI.Outs;
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auto &Caller = MF.getFunction();
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auto CallerCC = Caller.getCallingConv();
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// Do not tail call opt functions with "disable-tail-calls" attribute.
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if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true")
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return false;
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// Exception-handling functions need a special set of instructions to
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// indicate a return to the hardware. Tail-calling another function would
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// probably break this.
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// TODO: The "interrupt" attribute isn't currently defined by RISC-V. This
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// should be expanded as new function attributes are introduced.
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if (Caller.hasFnAttribute("interrupt"))
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return false;
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// Do not tail call opt functions with varargs.
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if (IsVarArg)
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return false;
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// Do not tail call opt if the stack is used to pass parameters.
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if (CCInfo.getNextStackOffset() != 0)
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return false;
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// Do not tail call opt if any parameters need to be passed indirectly.
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// Since long doubles (fp128) and i128 are larger than 2*XLEN, they are
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// passed indirectly. So the address of the value will be passed in a
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// register, or if not available, then the address is put on the stack. In
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// order to pass indirectly, space on the stack often needs to be allocated
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// in order to store the value. In this case the CCInfo.getNextStackOffset()
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// != 0 check is not enough and we need to check if any CCValAssign ArgsLocs
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// are passed CCValAssign::Indirect.
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for (auto &VA : ArgLocs)
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if (VA.getLocInfo() == CCValAssign::Indirect)
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return false;
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// Do not tail call opt if either caller or callee uses struct return
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// semantics.
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auto IsCallerStructRet = Caller.hasStructRetAttr();
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auto IsCalleeStructRet = Outs.empty() ? false : Outs[0].Flags.isSRet();
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if (IsCallerStructRet || IsCalleeStructRet)
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return false;
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// Externally-defined functions with weak linkage should not be
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// tail-called. The behaviour of branch instructions in this situation (as
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// used for tail calls) is implementation-defined, so we cannot rely on the
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// linker replacing the tail call with a return.
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if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
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const GlobalValue *GV = G->getGlobal();
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if (GV->hasExternalWeakLinkage())
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return false;
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}
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// The callee has to preserve all registers the caller needs to preserve.
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const RISCVRegisterInfo *TRI = Subtarget.getRegisterInfo();
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const uint32_t *CallerPreserved = TRI->getCallPreservedMask(MF, CallerCC);
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if (CalleeCC != CallerCC) {
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const uint32_t *CalleePreserved = TRI->getCallPreservedMask(MF, CalleeCC);
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if (!TRI->regmaskSubsetEqual(CallerPreserved, CalleePreserved))
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return false;
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}
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// Byval parameters hand the function a pointer directly into the stack area
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// we want to reuse during a tail call. Working around this *is* possible
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// but less efficient and uglier in LowerCall.
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for (auto &Arg : Outs)
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if (Arg.Flags.isByVal())
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return false;
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return true;
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}
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// Lower a call to a callseq_start + CALL + callseq_end chain, and add input
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// and output parameter nodes.
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SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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@ -1087,7 +1172,7 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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CLI.IsTailCall = false;
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bool &IsTailCall = CLI.IsTailCall;
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CallingConv::ID CallConv = CLI.CallConv;
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bool IsVarArg = CLI.IsVarArg;
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EVT PtrVT = getPointerTy(DAG.getDataLayout());
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@ -1100,6 +1185,17 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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CCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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analyzeOutputArgs(MF, ArgCCInfo, Outs, /*IsRet=*/false, &CLI);
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// Check if it's really possible to do a tail call.
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if (IsTailCall)
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IsTailCall = IsEligibleForTailCallOptimization(ArgCCInfo, CLI, MF,
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ArgLocs);
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if (IsTailCall)
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++NumTailCalls;
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else if (CLI.CS && CLI.CS.isMustTailCall())
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report_fatal_error("failed to perform tail call elimination on a call "
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"site marked musttail");
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// Get a count of how many bytes are to be pushed on the stack.
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unsigned NumBytes = ArgCCInfo.getNextStackOffset();
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@ -1121,11 +1217,12 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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Chain = DAG.getMemcpy(Chain, DL, FIPtr, Arg, SizeNode, Align,
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/*IsVolatile=*/false,
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/*AlwaysInline=*/false,
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/*isTailCall=*/false, MachinePointerInfo(),
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IsTailCall, MachinePointerInfo(),
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MachinePointerInfo());
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ByValArgs.push_back(FIPtr);
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}
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if (!IsTailCall)
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Chain = DAG.getCALLSEQ_START(Chain, NumBytes, 0, CLI.DL);
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// Copy argument values to their designated locations.
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@ -1213,6 +1310,8 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
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} else {
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assert(VA.isMemLoc() && "Argument not register or memory");
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assert(!IsTailCall && "Tail call not allowed if stack is used "
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"for passing parameters");
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// Work out the address of the stack slot.
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if (!StackPtr.getNode())
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@ -1258,11 +1357,13 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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for (auto &Reg : RegsToPass)
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Ops.push_back(DAG.getRegister(Reg.first, Reg.second.getValueType()));
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if (!IsTailCall) {
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// Add a register mask operand representing the call-preserved registers.
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const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
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const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
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assert(Mask && "Missing call preserved mask for calling convention");
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Ops.push_back(DAG.getRegisterMask(Mask));
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}
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// Glue the call to the argument copies, if any.
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if (Glue.getNode())
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@ -1270,6 +1371,12 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
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// Emit the call.
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SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
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if (IsTailCall) {
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MF.getFrameInfo().setHasTailCall();
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return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
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}
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Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
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Glue = Chain.getValue(1);
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@ -1425,6 +1532,8 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
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return "RISCVISD::BuildPairF64";
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case RISCVISD::SplitF64:
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return "RISCVISD::SplitF64";
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case RISCVISD::TAIL:
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return "RISCVISD::TAIL";
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}
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return nullptr;
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}
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@ -28,7 +28,8 @@ enum NodeType : unsigned {
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CALL,
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SELECT_CC,
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BuildPairF64,
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SplitF64
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SplitF64,
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TAIL
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};
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}
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@ -100,6 +101,10 @@ private:
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
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bool IsEligibleForTailCallOptimization(CCState &CCInfo,
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CallLoweringInfo &CLI, MachineFunction &MF,
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const SmallVector<CCValAssign, 16> &ArgLocs) const;
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};
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}
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@ -437,6 +437,7 @@ unsigned RISCVInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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case TargetOpcode::DBG_VALUE:
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return 0;
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case RISCV::PseudoCALL:
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case RISCV::PseudoTAIL:
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return 8;
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case TargetOpcode::INLINEASM: {
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const MachineFunction &MF = *MI.getParent()->getParent();
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@ -38,6 +38,9 @@ def RetFlag : SDNode<"RISCVISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
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def SelectCC : SDNode<"RISCVISD::SELECT_CC", SDT_RISCVSelectCC,
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[SDNPInGlue]>;
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def Tail : SDNode<"RISCVISD::TAIL", SDT_RISCVCall,
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[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
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SDNPVariadic]>;
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//===----------------------------------------------------------------------===//
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// Operand and SDNode transformation definitions.
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@ -665,11 +668,20 @@ def PseudoRET : Pseudo<(outs), (ins), [(RetFlag)]>,
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// expand to auipc and jalr while encoding.
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// Define AsmString to print "tail" when compile with -S flag.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2],
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hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0 in
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isCodeGenOnly = 0 in
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def PseudoTAIL : Pseudo<(outs), (ins bare_symbol:$dst), []> {
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let AsmString = "tail\t$dst";
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}
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [X2] in
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def PseudoTAILIndirect : Pseudo<(outs), (ins GPRTC:$rs1), [(Tail GPRTC:$rs1)]>,
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PseudoInstExpansion<(JALR X0, GPR:$rs1, 0)>;
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def : Pat<(Tail (iPTR tglobaladdr:$dst)),
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(PseudoTAIL texternalsym:$dst)>;
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def : Pat<(Tail (iPTR texternalsym:$dst)),
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(PseudoTAIL texternalsym:$dst)>;
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/// Loads
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multiclass LdPat<PatFrag LoadOp, RVInst Inst> {
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@ -139,6 +139,19 @@ def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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// For indirect tail calls, we can't use callee-saved registers, as they are
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// restored to the saved value before the tail call, which would clobber a call
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// address.
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def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
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(sequence "X%u", 5, 7),
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(sequence "X%u", 10, 17),
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(sequence "X%u", 28, 31)
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)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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[RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
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}
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def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
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let RegInfos = RegInfoByHwMode<
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[RV32, RV64, DefaultMode],
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@ -0,0 +1,56 @@
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; Check that command line option "-disable-tail-calls" overrides function
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; attribute "disable-tail-calls".
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; RUN: llc < %s -mtriple=riscv32-unknown-elf \
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; RUN: | FileCheck %s --check-prefixes=CALLER1,NOTAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls \
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; RUN: | FileCheck %s --check-prefixes=CALLER1,NOTAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls=false \
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; RUN: | FileCheck %s --check-prefixes=CALLER1,TAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf \
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; RUN: | FileCheck %s --check-prefixes=CALLER2,TAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls \
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; RUN: | FileCheck %s --check-prefixes=CALLER2,NOTAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls=false \
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; RUN: | FileCheck %s --check-prefixes=CALLER2,TAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf \
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; RUN: | FileCheck %s --check-prefixes=CALLER3,TAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls \
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; RUN: | FileCheck %s --check-prefixes=CALLER3,NOTAIL
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; RUN: llc < %s -mtriple=riscv32-unknown-elf -disable-tail-calls=false \
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; RUN: | FileCheck %s --check-prefixes=CALLER3,TAIL
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; CALLER1-LABEL: {{\_?}}caller1
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; CALLER2-LABEL: {{\_?}}caller2
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; CALLER3-LABEL: {{\_?}}caller3
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; NOTAIL-NOT: tail callee
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; NOTAIL: call callee
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; TAIL: tail callee
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; TAIL-NOT: call callee
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; Function with attribute #0 = { "disable-tail-calls"="true" }
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define i32 @caller1(i32 %a) #0 {
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entry:
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%call = tail call i32 @callee(i32 %a)
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ret i32 %call
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}
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; Function with attribute #1 = { "disable-tail-calls"="false" }
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define i32 @caller2(i32 %a) #0 {
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entry:
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%call = tail call i32 @callee(i32 %a)
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ret i32 %call
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}
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define i32 @caller3(i32 %a) {
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entry:
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%call = tail call i32 @callee(i32 %a)
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ret i32 %call
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}
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declare i32 @callee(i32)
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attributes #0 = { "disable-tail-calls"="true" }
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attributes #1 = { "disable-tail-calls"="false" }
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@ -0,0 +1,20 @@
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; Check that we error out if tail is not possible but call is marked as mustail.
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; RUN: not llc -mtriple riscv32-unknown-linux-gnu -o - %s \
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; RUN: 2>&1 | FileCheck %s
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; RUN: not llc -mtriple riscv32-unknown-elf -o - %s \
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; RUN: 2>&1 | FileCheck %s
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; RUN: not llc -mtriple riscv64-unknown-linux-gnu -o - %s \
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; RUN: 2>&1 | FileCheck %s
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; RUN: not llc -mtriple riscv64-unknown-elf -o - %s \
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; RUN: 2>&1 | FileCheck %s
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%struct.A = type { i32 }
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declare void @callee_musttail(%struct.A* sret %a)
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define void @caller_musttail(%struct.A* sret %a) {
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; CHECK: LLVM ERROR: failed to perform tail call elimination on a call site marked musttail
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entry:
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musttail call void @callee_musttail(%struct.A* sret %a)
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ret void
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}
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@ -0,0 +1,148 @@
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; RUN: llc -mtriple riscv32-unknown-linux-gnu -o - %s | FileCheck %s
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; RUN: llc -mtriple riscv32-unknown-elf -o - %s | FileCheck %s
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; Perform tail call optimization for global address.
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declare i32 @callee_tail(i32 %i)
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define i32 @caller_tail(i32 %i) {
|
||||
; CHECK-LABEL: caller_tail
|
||||
; CHECK: tail callee_tail
|
||||
entry:
|
||||
%r = tail call i32 @callee_tail(i32 %i)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Perform tail call optimization for external symbol.
|
||||
@dest = global [2 x i8] zeroinitializer
|
||||
declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i1)
|
||||
define void @caller_extern(i8* %src) optsize {
|
||||
entry:
|
||||
; CHECK: caller_extern
|
||||
; CHECK-NOT: call memcpy
|
||||
; CHECK: tail memcpy
|
||||
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([2 x i8], [2 x i8]* @dest, i32 0, i32 0), i8* %src, i32 7, i1 false)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Perform indirect tail call optimization (for function pointer call).
|
||||
declare void @callee_indirect1()
|
||||
declare void @callee_indirect2()
|
||||
define void @caller_indirect_tail(i32 %a) {
|
||||
; CHECK-LABEL: caller_indirect_tail
|
||||
; CHECK-NOT: call callee_indirect1
|
||||
; CHECK-NOT: call callee_indirect2
|
||||
; CHECK-NOT: tail callee_indirect1
|
||||
; CHECK-NOT: tail callee_indirect2
|
||||
|
||||
; CHECK: lui a0, %hi(callee_indirect2)
|
||||
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect2)
|
||||
; CHECK-NEXT: jr a5
|
||||
|
||||
; CHECK: lui a0, %hi(callee_indirect1)
|
||||
; CHECK-NEXT: addi a5, a0, %lo(callee_indirect1)
|
||||
; CHECK-NEXT: jr a5
|
||||
entry:
|
||||
%tobool = icmp eq i32 %a, 0
|
||||
%callee = select i1 %tobool, void ()* @callee_indirect1, void ()* @callee_indirect2
|
||||
tail call void %callee()
|
||||
ret void
|
||||
}
|
||||
|
||||
; Do not tail call optimize functions with varargs.
|
||||
declare i32 @callee_varargs(i32, ...)
|
||||
define void @caller_varargs(i32 %a, i32 %b) {
|
||||
; CHECK-LABEL: caller_varargs
|
||||
; CHECK-NOT: tail callee_varargs
|
||||
; CHECK: call callee_varargs
|
||||
entry:
|
||||
%call = tail call i32 (i32, ...) @callee_varargs(i32 %a, i32 %b, i32 %b, i32 %a)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Do not tail call optimize if stack is used to pass parameters.
|
||||
declare i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
|
||||
define i32 @caller_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n) {
|
||||
; CHECK-LABEL: caller_args
|
||||
; CHECK-NOT: tail callee_args
|
||||
; CHECK: call callee_args
|
||||
entry:
|
||||
%r = tail call i32 @callee_args(i32 %a, i32 %b, i32 %c, i32 %dd, i32 %e, i32 %ff, i32 %g, i32 %h, i32 %i, i32 %j, i32 %k, i32 %l, i32 %m, i32 %n)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Do not tail call optimize if parameters need to be passed indirectly.
|
||||
declare i32 @callee_indirect_args(fp128 %a)
|
||||
define void @caller_indirect_args() {
|
||||
; CHECK-LABEL: caller_indirect_args
|
||||
; CHECK-NOT: tail callee_indirect_args
|
||||
; CHECK: call callee_indirect_args
|
||||
entry:
|
||||
%call = tail call i32 @callee_indirect_args(fp128 0xL00000000000000003FFF000000000000)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Externally-defined functions with weak linkage should not be tail-called.
|
||||
; The behaviour of branch instructions in this situation (as used for tail
|
||||
; calls) is implementation-defined, so we cannot rely on the linker replacing
|
||||
; the tail call with a return.
|
||||
declare extern_weak void @callee_weak()
|
||||
define void @caller_weak() {
|
||||
; CHECK-LABEL: caller_weak
|
||||
; CHECK-NOT: tail callee_weak
|
||||
; CHECK: call callee_weak
|
||||
entry:
|
||||
tail call void @callee_weak()
|
||||
ret void
|
||||
}
|
||||
|
||||
; Exception-handling functions need a special set of instructions to indicate a
|
||||
; return to the hardware. Tail-calling another function would probably break
|
||||
; this.
|
||||
declare void @callee_irq()
|
||||
define void @caller_irq() #0 {
|
||||
; CHECK-LABEL: caller_irq
|
||||
; CHECK-NOT: tail callee_irq
|
||||
; CHECK: call callee_irq
|
||||
entry:
|
||||
tail call void @callee_irq()
|
||||
ret void
|
||||
}
|
||||
attributes #0 = { "interrupt" }
|
||||
|
||||
; Byval parameters hand the function a pointer directly into the stack area
|
||||
; we want to reuse during a tail call. Do not tail call optimize functions with
|
||||
; byval parameters.
|
||||
declare i32 @callee_byval(i32** byval %a)
|
||||
define i32 @caller_byval() {
|
||||
; CHECK-LABEL: caller_byval
|
||||
; CHECK-NOT: tail callee_byval
|
||||
; CHECK: call callee_byval
|
||||
entry:
|
||||
%a = alloca i32*
|
||||
%r = tail call i32 @callee_byval(i32** byval %a)
|
||||
ret i32 %r
|
||||
}
|
||||
|
||||
; Do not tail call optimize if callee uses structret semantics.
|
||||
%struct.A = type { i32 }
|
||||
@a = global %struct.A zeroinitializer
|
||||
|
||||
declare void @callee_struct(%struct.A* sret %a)
|
||||
define void @caller_nostruct() {
|
||||
; CHECK-LABEL: caller_nostruct
|
||||
; CHECK-NOT: tail callee_struct
|
||||
; CHECK: call callee_struct
|
||||
entry:
|
||||
tail call void @callee_struct(%struct.A* sret @a)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Do not tail call optimize if caller uses structret semantics.
|
||||
declare void @callee_nostruct()
|
||||
define void @caller_struct(%struct.A* sret %a) {
|
||||
; CHECK-LABEL: caller_struct
|
||||
; CHECK-NOT: tail callee_nostruct
|
||||
; CHECK: call callee_nostruct
|
||||
entry:
|
||||
tail call void @callee_nostruct()
|
||||
ret void
|
||||
}
|
||||
Loading…
Reference in New Issue