forked from OSchip/llvm-project
[MachineCombiner, AArch64] Add a new pattern A-(B+C) => (A-B)-C to reduce latency
Add a new pattern A - (B + C) ==> (A - B) - C to give machine combiner a chance to evaluate which instruction sequence has lower latency. Differential Revision: https://reviews.llvm.org/D124564
This commit is contained in:
Guozhi Wei
parent
906f52f2c4
commit
ddc9e8861c
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@ -34,6 +34,10 @@ enum class MachineCombinerPattern {
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REASSOC_XY_BCA,
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REASSOC_XY_BAC,
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// These are patterns used to reduce the length of dependence chain.
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SUBADD_OP1,
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SUBADD_OP2,
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// These are multiply-add patterns matched by the AArch64 machine combiner.
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MULADDW_OP1,
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MULADDW_OP2,
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@ -277,6 +277,8 @@ static CombinerObjective getCombinerObjective(MachineCombinerPattern P) {
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case MachineCombinerPattern::REASSOC_XA_YB:
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case MachineCombinerPattern::REASSOC_XY_AMM_BMM:
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case MachineCombinerPattern::REASSOC_XMM_AMM_BMM:
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case MachineCombinerPattern::SUBADD_OP1:
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case MachineCombinerPattern::SUBADD_OP2:
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return CombinerObjective::MustReduceDepth;
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case MachineCombinerPattern::REASSOC_XY_BCA:
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case MachineCombinerPattern::REASSOC_XY_BAC:
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@ -4866,6 +4866,10 @@ static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
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return false;
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}
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if (isCombineInstrSettingFlag(CombineOpc) &&
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MI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
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return false;
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return true;
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}
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@ -5366,6 +5370,42 @@ bool AArch64InstrInfo::isThroughputPattern(
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} // end switch (Pattern)
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return false;
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}
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/// Find other MI combine patterns.
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static bool getMiscPatterns(MachineInstr &Root,
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SmallVectorImpl<MachineCombinerPattern> &Patterns)
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{
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// A - (B + C) ==> (A - B) - C or (A - C) - B
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unsigned Opc = Root.getOpcode();
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MachineBasicBlock &MBB = *Root.getParent();
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switch (Opc) {
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case AArch64::SUBWrr:
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case AArch64::SUBSWrr:
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case AArch64::SUBXrr:
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case AArch64::SUBSXrr:
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// Found candidate root.
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break;
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default:
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return false;
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}
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if (isCombineInstrSettingFlag(Opc) &&
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Root.findRegisterDefOperandIdx(AArch64::NZCV, true) == -1)
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return false;
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if (canCombine(MBB, Root.getOperand(2), AArch64::ADDWrr) ||
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canCombine(MBB, Root.getOperand(2), AArch64::ADDSWrr) ||
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canCombine(MBB, Root.getOperand(2), AArch64::ADDXrr) ||
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canCombine(MBB, Root.getOperand(2), AArch64::ADDSXrr)) {
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Patterns.push_back(MachineCombinerPattern::SUBADD_OP1);
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Patterns.push_back(MachineCombinerPattern::SUBADD_OP2);
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return true;
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}
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return false;
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}
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/// Return true when there is potentially a faster code sequence for an
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/// instruction chain ending in \p Root. All potential patterns are listed in
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/// the \p Pattern vector. Pattern should be sorted in priority order since the
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@ -5383,6 +5423,10 @@ bool AArch64InstrInfo::getMachineCombinerPatterns(
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if (getFMAPatterns(Root, Patterns))
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return true;
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// Other patterns
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if (getMiscPatterns(Root, Patterns))
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return true;
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return TargetInstrInfo::getMachineCombinerPatterns(Root, Patterns,
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DoRegPressureReduce);
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}
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@ -5633,6 +5677,53 @@ static MachineInstr *genMaddR(MachineFunction &MF, MachineRegisterInfo &MRI,
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return MUL;
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}
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/// Do the following transformation
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/// A - (B + C) ==> (A - B) - C
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/// A - (B + C) ==> (A - C) - B
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static void
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genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
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const TargetInstrInfo *TII, MachineInstr &Root,
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SmallVectorImpl<MachineInstr *> &InsInstrs,
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SmallVectorImpl<MachineInstr *> &DelInstrs,
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unsigned IdxOpd1,
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DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) {
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assert(IdxOpd1 == 1 || IdxOpd1 == 2);
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unsigned IdxOtherOpd = IdxOpd1 == 1 ? 2 : 1;
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MachineInstr *AddMI = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
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Register ResultReg = Root.getOperand(0).getReg();
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Register RegA = Root.getOperand(1).getReg();
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bool RegAIsKill = Root.getOperand(1).isKill();
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Register RegB = AddMI->getOperand(IdxOpd1).getReg();
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bool RegBIsKill = AddMI->getOperand(IdxOpd1).isKill();
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Register RegC = AddMI->getOperand(IdxOtherOpd).getReg();
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bool RegCIsKill = AddMI->getOperand(IdxOtherOpd).isKill();
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Register NewVR = MRI.createVirtualRegister(MRI.getRegClass(RegA));
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unsigned Opcode = Root.getOpcode();
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if (Opcode == AArch64::SUBSWrr)
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Opcode = AArch64::SUBWrr;
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else if (Opcode == AArch64::SUBSXrr)
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Opcode = AArch64::SUBXrr;
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else
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assert((Opcode == AArch64::SUBWrr || Opcode == AArch64::SUBXrr) &&
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"Unexpected instruction opcode.");
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MachineInstrBuilder MIB1 =
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BuildMI(MF, Root.getDebugLoc(), TII->get(Opcode), NewVR)
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.addReg(RegA, getKillRegState(RegAIsKill))
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.addReg(RegB, getKillRegState(RegBIsKill));
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MachineInstrBuilder MIB2 =
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BuildMI(MF, Root.getDebugLoc(), TII->get(Opcode), ResultReg)
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.addReg(NewVR, getKillRegState(true))
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.addReg(RegC, getKillRegState(RegCIsKill));
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InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
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InsInstrs.push_back(MIB1);
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InsInstrs.push_back(MIB2);
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DelInstrs.push_back(AddMI);
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}
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/// When getMachineCombinerPatterns() finds potential patterns,
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/// this function generates the instructions that could replace the
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/// original code sequence
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@ -5655,6 +5746,18 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
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TargetInstrInfo::genAlternativeCodeSequence(Root, Pattern, InsInstrs,
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DelInstrs, InstrIdxForVirtReg);
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return;
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case MachineCombinerPattern::SUBADD_OP1:
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// A - (B + C)
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// ==> (A - B) - C
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genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 1,
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InstrIdxForVirtReg);
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break;
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case MachineCombinerPattern::SUBADD_OP2:
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// A - (B + C)
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// ==> (A - C) - B
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genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 2,
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InstrIdxForVirtReg);
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break;
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case MachineCombinerPattern::MULADDW_OP1:
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case MachineCombinerPattern::MULADDX_OP1:
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// MUL I=A,B,0
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@ -0,0 +1,76 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu %s -o - | FileCheck %s
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; The test cases in this file check following transformation if the right form
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; can reduce latency.
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; A - (B + C) ==> (A - B) - C
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; 32 bit version.
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define i32 @test1(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w9, w0, #100
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; CHECK-NEXT: orr w8, w2, #0x80
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; CHECK-NEXT: sub w8, w8, w9
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; CHECK-NEXT: eor w9, w1, w9, lsl #8
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; CHECK-NEXT: sub w8, w8, w9
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; CHECK-NEXT: eor w0, w8, w9, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i32 %c, 128
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%a1 = add i32 %a, 100
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%shl = shl i32 %a1, 8
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%xor = xor i32 %shl, %b
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%add = add i32 %xor, %a1
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%sub = sub i32 %c1, %add
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%shr = ashr i32 %xor, 13
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%xor2 = xor i32 %sub, %shr
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ret i32 %xor2
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}
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; 64 bit version.
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define i64 @test2(i64 %a, i64 %b, i64 %c) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add x9, x0, #100
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; CHECK-NEXT: orr x8, x2, #0x80
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; CHECK-NEXT: sub x8, x8, x9
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; CHECK-NEXT: eor x9, x1, x9, lsl #8
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; CHECK-NEXT: sub x8, x8, x9
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; CHECK-NEXT: eor x0, x8, x9, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i64 %c, 128
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%a1 = add i64 %a, 100
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%shl = shl i64 %a1, 8
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%xor = xor i64 %shl, %b
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%add = add i64 %xor, %a1
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%sub = sub i64 %c1, %add
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%shr = ashr i64 %xor, 13
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%xor2 = xor i64 %sub, %shr
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ret i64 %xor2
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}
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; Negative test. The right form can't reduce latency.
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define i32 @test3(i32 %a, i32 %b, i32 %c) {
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; CHECK-LABEL: test3:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w9, w0, #100
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; CHECK-NEXT: orr w8, w2, #0x80
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; CHECK-NEXT: add w8, w8, w9
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; CHECK-NEXT: eor w9, w1, w9, lsl #8
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; CHECK-NEXT: sub w8, w9, w8
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; CHECK-NEXT: eor w0, w8, w9, asr #13
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; CHECK-NEXT: ret
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entry:
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%c1 = or i32 %c, 128
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%a1 = add i32 %a, 100
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%shl = shl i32 %a1, 8
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%xor = xor i32 %shl, %b
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%add = add i32 %c1, %a1
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%sub = sub i32 %xor, %add
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%shr = ashr i32 %xor, 13
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%xor2 = xor i32 %sub, %shr
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ret i32 %xor2
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}
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@ -0,0 +1,239 @@
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# RUN: llc -mtriple=aarch64-linux-gnu -run-pass machine-combiner -o - %s | FileCheck %s
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# The test cases in this file check following transformation if the right form
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# can reduce latency.
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# A - (B + C) ==> (A - B) - C
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---
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# 32 bit.
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# CHECK-LABEL: name: test1
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# CHECK: %10:gpr32common = SUBWrr killed %3, %4
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# CHECK-NEXT: %7:gpr32 = SUBWrr killed %10, %5
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name: test1
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registers:
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- { id: 0, class: gpr32common }
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- { id: 1, class: gpr32 }
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- { id: 2, class: gpr32 }
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- { id: 3, class: gpr32common }
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- { id: 4, class: gpr32common }
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- { id: 5, class: gpr32 }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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- { id: 8, class: gpr32 }
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body: |
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bb.0:
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%2:gpr32 = COPY $w2
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%1:gpr32 = COPY $w1
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%0:gpr32common = COPY $w0
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%3:gpr32common = ORRWri %2:gpr32, 1600
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%4:gpr32common = ADDWri %0:gpr32common, 100, 0
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%5:gpr32 = EORWrs %1:gpr32, %4:gpr32common, 8
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%6:gpr32 = ADDWrr %5:gpr32, %4:gpr32common
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%7:gpr32 = SUBWrr killed %3:gpr32common, killed %6:gpr32
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%8:gpr32 = EORWrs killed %7:gpr32, %5:gpr32, 141
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$w0 = COPY %8:gpr32
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RET_ReallyLR implicit $w0
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...
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---
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# 64 bit.
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# CHECK-LABEL: name: test2
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# CHECK: %10:gpr64common = SUBXrr killed %3, %4
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# CHECK-NEXT: %7:gpr64 = SUBXrr killed %10, %5
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name: test2
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registers:
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- { id: 0, class: gpr64common }
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- { id: 1, class: gpr64 }
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- { id: 2, class: gpr64 }
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- { id: 3, class: gpr64common }
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- { id: 4, class: gpr64common }
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- { id: 5, class: gpr64 }
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- { id: 6, class: gpr64 }
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- { id: 7, class: gpr64 }
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- { id: 8, class: gpr64 }
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body: |
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bb.0:
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%2:gpr64 = COPY $x2
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%1:gpr64 = COPY $x1
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%0:gpr64common = COPY $x0
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%3:gpr64common = ORRXri %2:gpr64, 1600
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%4:gpr64common = ADDXri %0:gpr64common, 100, 0
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%5:gpr64 = EORXrs %1:gpr64, %4:gpr64common, 8
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%6:gpr64 = ADDXrr %5:gpr64, %4:gpr64common
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%7:gpr64 = SUBXrr killed %3:gpr64common, killed %6:gpr64
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%8:gpr64 = EORXrs killed %7:gpr64, %5:gpr64, 141
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$x0 = COPY %8:gpr64
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RET_ReallyLR implicit $x0
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...
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---
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# Negative test. The right form can't reduce latency.
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# CHECK-LABEL: name: test3
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# CHECK: %6:gpr32 = ADDWrr killed %3, %4
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# CHECK-NEXT: %7:gpr32 = SUBWrr %5, killed %6
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name: test3
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registers:
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- { id: 0, class: gpr32common }
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- { id: 1, class: gpr32 }
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- { id: 2, class: gpr32 }
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- { id: 3, class: gpr32common }
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- { id: 4, class: gpr32common }
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- { id: 5, class: gpr32 }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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- { id: 8, class: gpr32 }
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body: |
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bb.0:
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%2:gpr32 = COPY $w2
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%1:gpr32 = COPY $w1
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%0:gpr32common = COPY $w0
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%3:gpr32common = ORRWri %2:gpr32, 1600
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%4:gpr32common = ADDWri %0:gpr32common, 100, 0
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%5:gpr32 = EORWrs %1:gpr32, %4:gpr32common, 8
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%6:gpr32 = ADDWrr killed %3:gpr32common, %4:gpr32common
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%7:gpr32 = SUBWrr %5:gpr32, killed %6:gpr32
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%8:gpr32 = EORWrs killed %7:gpr32, %5:gpr32, 141
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$w0 = COPY %8:gpr32
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RET_ReallyLR implicit $w0
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...
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---
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# Dead define of flag registers should not block transformation.
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# CHECK-LABEL: name: test4
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# CHECK: %10:gpr64common = SUBXrr killed %3, %4
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# CHECK-NEXT: %7:gpr64 = SUBXrr killed %10, %5
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name: test4
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registers:
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- { id: 0, class: gpr64common }
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- { id: 1, class: gpr64 }
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- { id: 2, class: gpr64 }
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- { id: 3, class: gpr64common }
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- { id: 4, class: gpr64common }
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- { id: 5, class: gpr64 }
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- { id: 6, class: gpr64 }
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- { id: 7, class: gpr64 }
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- { id: 8, class: gpr64 }
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body: |
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bb.0:
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%2:gpr64 = COPY $x2
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%1:gpr64 = COPY $x1
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%0:gpr64common = COPY $x0
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%3:gpr64common = ORRXri %2:gpr64, 1600
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%4:gpr64common = ADDXri %0:gpr64common, 100, 0
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%5:gpr64 = EORXrs %1:gpr64, %4:gpr64common, 8
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%6:gpr64 = ADDSXrr %5:gpr64, %4:gpr64common, implicit-def dead $nzcv
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%7:gpr64 = SUBSXrr killed %3:gpr64common, killed %6:gpr64, implicit-def dead $nzcv
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%8:gpr64 = EORXrs killed %7:gpr64, %5:gpr64, 141
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$x0 = COPY %8:gpr64
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RET_ReallyLR implicit $x0
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...
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---
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# Non dead define of flag register in SUB can block the transformation.
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# CHECK-LABEL: name: test5
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# CHECK: %6:gpr32 = ADDWrr %5, %4
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# CHECK-NEXT: %7:gpr32 = SUBSWrr killed %3, killed %6, implicit-def $nzcv
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name: test5
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registers:
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- { id: 0, class: gpr32common }
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- { id: 1, class: gpr32 }
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- { id: 2, class: gpr32 }
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- { id: 3, class: gpr32common }
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- { id: 4, class: gpr32common }
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- { id: 5, class: gpr32 }
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- { id: 6, class: gpr32 }
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- { id: 7, class: gpr32 }
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- { id: 8, class: gpr32 }
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body: |
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bb.0:
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%2:gpr32 = COPY $w2
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%1:gpr32 = COPY $w1
|
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%0:gpr32common = COPY $w0
|
||||
%3:gpr32common = ORRWri %2:gpr32, 1600
|
||||
%4:gpr32common = ADDWri %0:gpr32common, 100, 0
|
||||
%5:gpr32 = EORWrs %1:gpr32, %4:gpr32common, 8
|
||||
%6:gpr32 = ADDWrr %5:gpr32, %4:gpr32common
|
||||
%7:gpr32 = SUBSWrr killed %3:gpr32common, killed %6:gpr32, implicit-def $nzcv
|
||||
%8:gpr32 = EORWrs killed %7:gpr32, %5:gpr32, 141
|
||||
$w0 = COPY %8:gpr32
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
---
|
||||
# Non dead define of flag register in ADD can block the transformation.
|
||||
|
||||
# CHECK-LABEL: name: test6
|
||||
# CHECK: %6:gpr64 = ADDSXrr %5, %4, implicit-def $nzcv
|
||||
# CHECK-NEXT: %7:gpr64 = SUBXrr killed %3, killed %6
|
||||
|
||||
name: test6
|
||||
registers:
|
||||
- { id: 0, class: gpr64common }
|
||||
- { id: 1, class: gpr64 }
|
||||
- { id: 2, class: gpr64 }
|
||||
- { id: 3, class: gpr64common }
|
||||
- { id: 4, class: gpr64common }
|
||||
- { id: 5, class: gpr64 }
|
||||
- { id: 6, class: gpr64 }
|
||||
- { id: 7, class: gpr64 }
|
||||
- { id: 8, class: gpr64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%2:gpr64 = COPY $x2
|
||||
%1:gpr64 = COPY $x1
|
||||
%0:gpr64common = COPY $x0
|
||||
%3:gpr64common = ORRXri %2:gpr64, 1600
|
||||
%4:gpr64common = ADDXri %0:gpr64common, 100, 0
|
||||
%5:gpr64 = EORXrs %1:gpr64, %4:gpr64common, 8
|
||||
%6:gpr64 = ADDSXrr %5:gpr64, %4:gpr64common, implicit-def $nzcv
|
||||
%7:gpr64 = SUBXrr killed %3:gpr64common, killed %6:gpr64
|
||||
%8:gpr64 = EORXrs killed %7:gpr64, %5:gpr64, 141
|
||||
$x0 = COPY %8:gpr64
|
||||
RET_ReallyLR implicit $x0
|
||||
|
||||
...
|
||||
---
|
||||
# ADD has multiple uses, so it is always required, we should not transform it.
|
||||
|
||||
# CHECK-LABEL: name: test7
|
||||
# CHECK: %6:gpr32 = ADDWrr %5, %4
|
||||
# CHECK-NEXT: %7:gpr32 = SUBWrr killed %3, %6
|
||||
|
||||
name: test7
|
||||
registers:
|
||||
- { id: 0, class: gpr32common }
|
||||
- { id: 1, class: gpr32 }
|
||||
- { id: 2, class: gpr32 }
|
||||
- { id: 3, class: gpr32common }
|
||||
- { id: 4, class: gpr32common }
|
||||
- { id: 5, class: gpr32 }
|
||||
- { id: 6, class: gpr32 }
|
||||
- { id: 7, class: gpr32 }
|
||||
- { id: 8, class: gpr32 }
|
||||
- { id: 9, class: gpr32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%2:gpr32 = COPY $w2
|
||||
%1:gpr32 = COPY $w1
|
||||
%0:gpr32common = COPY $w0
|
||||
%3:gpr32common = ORRWri %2:gpr32, 1600
|
||||
%4:gpr32common = ADDWri %0:gpr32common, 100, 0
|
||||
%5:gpr32 = EORWrs %1:gpr32, %4:gpr32common, 8
|
||||
%6:gpr32 = ADDWrr %5:gpr32, %4:gpr32common
|
||||
%7:gpr32 = SUBWrr killed %3:gpr32common, %6:gpr32
|
||||
%8:gpr32 = EORWrs killed %7:gpr32, %5:gpr32, 141
|
||||
%9:gpr32 = ADDWrr %8:gpr32, %6:gpr32
|
||||
$w0 = COPY %9:gpr32
|
||||
RET_ReallyLR implicit $w0
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue