forked from OSchip/llvm-project
[ARM][llvm-objdump] Annotate PC-relative memory operands
This implements `MCInstrAnalysis::evaluateMemoryOperandAddress()` for Arm so that the disassembler can print the target address of memory operands that use PC+immediate addressing. Differential Revision: https://reviews.llvm.org/D105979
This commit is contained in:
Igor Kudrin
parent
00809c8889
commit
ddbe812bcc
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@ -1385,8 +1385,8 @@ class ThumbXI<dag oops, dag iops, AddrMode am, int sz,
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}
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class T2I<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeNone, 4, itin, opc, asm, "", pattern>;
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string opc, string asm, list<dag> pattern, AddrMode am = AddrModeNone>
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: Thumb2I<oops, iops, am, 4, itin, opc, asm, "", pattern>;
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class T2Ii12<dag oops, dag iops, InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: Thumb2I<oops, iops, AddrModeT2_i12, 4, itin, opc, asm, "",pattern>;
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@ -5391,14 +5391,16 @@ def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
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}
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class ACI<dag oops, dag iops, string opc, string asm,
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list<dag> pattern, IndexMode im = IndexModeNone>
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: I<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
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list<dag> pattern, IndexMode im = IndexModeNone,
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AddrMode am = AddrModeNone>
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: I<oops, iops, am, 4, im, BrFrm, NoItinerary,
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opc, asm, "", pattern> {
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let Inst{27-25} = 0b110;
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}
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class ACInoP<dag oops, dag iops, string opc, string asm,
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list<dag> pattern, IndexMode im = IndexModeNone>
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: InoP<oops, iops, AddrModeNone, 4, im, BrFrm, NoItinerary,
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list<dag> pattern, IndexMode im = IndexModeNone,
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AddrMode am = AddrModeNone>
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: InoP<oops, iops, am, 4, im, BrFrm, NoItinerary,
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opc, asm, "", pattern> {
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let Inst{31-28} = 0b1111;
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let Inst{27-25} = 0b110;
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@ -5407,7 +5409,8 @@ class ACInoP<dag oops, dag iops, string opc, string asm,
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let DecoderNamespace = "CoProc" in {
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multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
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def _OFFSET : ACI<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr", pattern> {
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asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
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AddrMode5> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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@ -5478,7 +5481,8 @@ multiclass LdStCop<bit load, bit Dbit, string asm, list<dag> pattern> {
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}
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multiclass LdSt2Cop<bit load, bit Dbit, string asm, list<dag> pattern> {
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def _OFFSET : ACInoP<(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr", pattern> {
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asm, "\t$cop, $CRd, $addr", pattern, IndexModeNone,
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AddrMode5> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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@ -168,6 +168,7 @@ def thumb_cb_target : Operand<OtherVT> {
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let EncoderMethod = "getThumbCBTargetOpValue";
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let DecoderMethod = "DecodeThumbCmpBROperand";
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}
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} // OperandType = "OPERAND_PCREL"
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// t_addrmode_pc := <label> => pc + imm8 * 4
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//
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@ -177,7 +178,6 @@ def t_addrmode_pc : MemOperand {
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let PrintMethod = "printThumbLdrLabelOperand";
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let ParserMatchClass = ThumbMemPC;
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}
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}
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// t_addrmode_rr := reg + reg
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//
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@ -200,7 +200,7 @@ def t2addrmode_imm12 : MemOperand,
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}
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// t2ldrlabel := imm12
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def t2ldrlabel : Operand<i32> {
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def t2ldrlabel : MemOperand {
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let EncoderMethod = "getAddrModeImm12OpValue";
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let PrintMethod = "printThumbLdrLabelOperand";
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}
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@ -1927,7 +1927,7 @@ def : InstAlias<"pli${p}.w\t$addr",
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// pci variant is very similar to i12, but supports negative offsets
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// from the PC. Only PLD and PLI have pci variants (not PLDW)
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class T2Iplpci<bits<1> inst, string opc> : T2Iso<(outs), (ins t2ldrlabel:$addr),
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class T2Iplpci<bits<1> inst, string opc> : T2Ipc<(outs), (ins t2ldrlabel:$addr),
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IIC_Preload, opc, "\t$addr",
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[(ARMPreload (ARMWrapper tconstpool:$addr),
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(i32 0), (i32 inst))]>, Sched<[WritePreLd]> {
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@ -4274,8 +4274,9 @@ def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src),
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//===----------------------------------------------------------------------===//
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// Coprocessor load/store -- for disassembly only
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//
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class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag> pattern>
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: T2I<oops, iops, NoItinerary, opc, asm, pattern> {
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class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm,
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list<dag> pattern, AddrMode am = AddrModeNone>
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: T2I<oops, iops, NoItinerary, opc, asm, pattern, am> {
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let Inst{31-28} = op31_28;
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let Inst{27-25} = 0b110;
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}
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@ -4283,7 +4284,7 @@ class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm, list<dag
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multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm, list<dag> pattern> {
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def _OFFSET : T2CI<op31_28,
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(outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr),
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asm, "\t$cop, $CRd, $addr", pattern> {
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asm, "\t$cop, $CRd, $addr", pattern, AddrMode5> {
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bits<13> addr;
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bits<4> cop;
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bits<4> CRd;
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@ -441,8 +441,173 @@ public:
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}
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return false;
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}
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Optional<uint64_t> evaluateMemoryOperandAddress(const MCInst &Inst,
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uint64_t Addr,
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uint64_t Size) const override;
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};
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} // namespace
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static Optional<uint64_t>
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// NOLINTNEXTLINE(readability-identifier-naming)
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evaluateMemOpAddrForAddrMode_i12(const MCInst &Inst, const MCInstrDesc &Desc,
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unsigned MemOpIndex, uint64_t Addr) {
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if (MemOpIndex + 1 >= Desc.getNumOperands())
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return None;
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const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
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const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
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if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
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return None;
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int32_t OffImm = (int32_t)MO2.getImm();
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// Special value for #-0. All others are normal.
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if (OffImm == INT32_MIN)
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OffImm = 0;
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return Addr + OffImm;
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}
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static Optional<uint64_t> evaluateMemOpAddrForAddrMode3(const MCInst &Inst,
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const MCInstrDesc &Desc,
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unsigned MemOpIndex,
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uint64_t Addr) {
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if (MemOpIndex + 2 >= Desc.getNumOperands())
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return None;
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const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
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const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
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const MCOperand &MO3 = Inst.getOperand(MemOpIndex + 2);
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if (!MO1.isReg() || MO1.getReg() != ARM::PC || MO2.getReg() || !MO3.isImm())
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return None;
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unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
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ARM_AM::AddrOpc Op = ARM_AM::getAM3Op(MO3.getImm());
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if (Op == ARM_AM::sub)
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return Addr - ImmOffs;
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return Addr + ImmOffs;
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}
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static Optional<uint64_t> evaluateMemOpAddrForAddrMode5(const MCInst &Inst,
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const MCInstrDesc &Desc,
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unsigned MemOpIndex,
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uint64_t Addr) {
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if (MemOpIndex + 1 >= Desc.getNumOperands())
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return None;
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const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
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const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
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if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
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return None;
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unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
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ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
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if (Op == ARM_AM::sub)
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return Addr - ImmOffs * 4;
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return Addr + ImmOffs * 4;
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}
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static Optional<uint64_t>
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// NOLINTNEXTLINE(readability-identifier-naming)
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evaluateMemOpAddrForAddrModeT2_i8s4(const MCInst &Inst, const MCInstrDesc &Desc,
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unsigned MemOpIndex, uint64_t Addr) {
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if (MemOpIndex + 1 >= Desc.getNumOperands())
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return None;
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const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
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const MCOperand &MO2 = Inst.getOperand(MemOpIndex + 1);
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if (!MO1.isReg() || MO1.getReg() != ARM::PC || !MO2.isImm())
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return None;
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int32_t OffImm = (int32_t)MO2.getImm();
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assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
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// Special value for #-0. All others are normal.
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if (OffImm == INT32_MIN)
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OffImm = 0;
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return Addr + OffImm;
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}
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static Optional<uint64_t>
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// NOLINTNEXTLINE(readability-identifier-naming)
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evaluateMemOpAddrForAddrModeT2_pc(const MCInst &Inst, const MCInstrDesc &Desc,
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unsigned MemOpIndex, uint64_t Addr) {
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const MCOperand &MO1 = Inst.getOperand(MemOpIndex);
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if (!MO1.isImm())
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return None;
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int32_t OffImm = (int32_t)MO1.getImm();
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// Special value for #-0. All others are normal.
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if (OffImm == INT32_MIN)
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OffImm = 0;
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return Addr + OffImm;
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}
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static Optional<uint64_t>
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// NOLINTNEXTLINE(readability-identifier-naming)
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evaluateMemOpAddrForAddrModeT1_s(const MCInst &Inst, const MCInstrDesc &Desc,
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unsigned MemOpIndex, uint64_t Addr) {
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return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, MemOpIndex, Addr);
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}
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Optional<uint64_t> ARMMCInstrAnalysis::evaluateMemoryOperandAddress(
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const MCInst &Inst, uint64_t Addr, uint64_t Size) const {
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const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
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// Only load instructions can have PC-relative memory addressing.
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if (!Desc.mayLoad())
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return None;
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// PC-relative addressing does not update the base register.
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uint64_t TSFlags = Desc.TSFlags;
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unsigned IndexMode =
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(TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
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if (IndexMode != ARMII::IndexModeNone)
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return None;
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// Find the memory addressing operand in the instruction.
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unsigned OpIndex = Desc.NumDefs;
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while (OpIndex < Desc.getNumOperands() &&
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Desc.OpInfo[OpIndex].OperandType != MCOI::OPERAND_MEMORY)
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++OpIndex;
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if (OpIndex == Desc.getNumOperands())
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return None;
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// Base address for PC-relative addressing is always 32-bit aligned.
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Addr &= ~0x3;
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// For ARM instructions the PC offset is 8 bytes, for Thumb instructions it
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// is 4 bytes.
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switch (Desc.TSFlags & ARMII::FormMask) {
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default:
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Addr += 8;
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break;
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case ARMII::ThumbFrm:
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Addr += 4;
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break;
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}
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// Eveluate the address depending on the addressing mode
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unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
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switch (AddrMode) {
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default:
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return None;
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case ARMII::AddrMode_i12:
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return evaluateMemOpAddrForAddrMode_i12(Inst, Desc, OpIndex, Addr);
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case ARMII::AddrMode3:
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return evaluateMemOpAddrForAddrMode3(Inst, Desc, OpIndex, Addr);
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case ARMII::AddrMode5:
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return evaluateMemOpAddrForAddrMode5(Inst, Desc, OpIndex, Addr);
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case ARMII::AddrModeT2_i8s4:
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return evaluateMemOpAddrForAddrModeT2_i8s4(Inst, Desc, OpIndex, Addr);
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case ARMII::AddrModeT2_pc:
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return evaluateMemOpAddrForAddrModeT2_pc(Inst, Desc, OpIndex, Addr);
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case ARMII::AddrModeT1_s:
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return evaluateMemOpAddrForAddrModeT1_s(Inst, Desc, OpIndex, Addr);
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}
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}
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static MCInstrAnalysis *createARMMCInstrAnalysis(const MCInstrInfo *Info) {
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@ -0,0 +1,66 @@
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@@ Check that PC-relative memory addressing is annotated
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@ RUN: llvm-mc %s -triple=armv7 -filetype=obj | \
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@ RUN: llvm-objdump -d --no-show-raw-insn --triple=armv7 - | \
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@ RUN: FileCheck %s
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.text
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foo:
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@ CHECK: 00000000 <foo>:
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.word 0x01020304
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_start:
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@ CHECK: 00000004 <_start>:
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@@ Check a special case immediate for AddrMode_i12
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ldr r1, [pc, #-0]
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@ CHECK-NEXT: 4: ldr r1, [pc, #-0] @ 0xc <_start+0x8>
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@@ Check AddrMode_i12 instructions, with positive and negative immediates
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ldr r0, foo
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ldrb r0, bar
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pli _start
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pld bar
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@ CHECK-NEXT: 8: ldr r0, [pc, #-16] @ 0x0 <foo>
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@ CHECK-NEXT: c: ldrb r0, [pc, #48] @ 0x44 <bar>
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@ CHECK-NEXT: 10: pli [pc, #-20] @ 0x4 <_start>
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@ CHECK-NEXT: 14: pld [pc, #40] @ 0x44 <bar>
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@@ Check that AddrMode_i12 instructions that do not use PC-relative addressing
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@@ are not annotated
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ldr r0, [r1, #8]
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@ CHECK-NEXT: 18: ldr r0, [r1, #8]{{$}}
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@@ Check AddrMode3 instructions, with positive and negative immediates
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ldrd r0, r1, foo
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ldrh r0, bar
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@ CHECK-NEXT: 1c: ldrd r0, r1, [pc, #-36] @ 0x0 <foo>
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@ CHECK-NEXT: 20: ldrh r0, [pc, #28] @ 0x44 <bar>
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@@ Check that AddrMode3 instruction that do not use PC+imm addressing are not
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@@ annotated
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ldrh r0, [r1, #8]
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ldrh r0, [pc, r2]
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@ CHECK-NEXT: 24: ldrh r0, [r1, #8]{{$}}
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@ CHECK-NEXT: 28: ldrh r0, [pc, r2]{{$}}
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@@ Check AddrMode5 instructions, with positive and negative immediates
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ldc p14, c5, foo
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ldcl p6, c4, bar
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ldc2 p5, c2, foo
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ldc2l p3, c1, bar
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@ CHECK-NEXT: 2c: ldc p14, c5, [pc, #-52] @ 0x0 <foo>
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@ CHECK-NEXT: 30: ldcl p6, c4, [pc, #12] @ 0x44 <bar>
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@ CHECK-NEXT: 34: ldc2 p5, c2, [pc, #-60] @ 0x0 <foo>
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@ CHECK-NEXT: 38: ldc2l p3, c1, [pc, #4] @ 0x44 <bar>
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@@ Check that AddrMode5 instruction that do not use PC+imm addressing are not
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@@ annotated
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ldc p14, c5, [r1, #8]
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ldc p14, c5, [pc], {16}
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@ CHECK-NEXT: 3c: ldc p14, c5, [r1, #8]{{$}}
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@ CHECK-NEXT: 40: ldc p14, c5, [pc], {16}{{$}}
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bar:
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@ CHECK: 00000044 <bar>:
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.word 0x01020304
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@ -0,0 +1,24 @@
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@@ Check that PC-relative memory addressing is annotated
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@ RUN: llvm-mc %s -triple=thumbv6m -filetype=obj | \
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@ RUN: llvm-objdump -d --no-show-raw-insn --triple=thumbv6m - | \
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@ RUN: FileCheck %s
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.text
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_start:
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@ CHECK: 00000000 <_start>:
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@@ Check AddrModeT1_s instruction, with 4-byte and 2-byte alignment
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ldr r0, bar
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ldr r1, bar
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ldr r2, bar
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ldr r3, bar
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@ CHECK-NEXT: 0: ldr r0, [pc, #4] @ 0x8 <bar>
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@ CHECK-NEXT: 2: ldr r1, [pc, #4] @ 0x8 <bar>
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@ CHECK-NEXT: 4: ldr r2, [pc, #0] @ 0x8 <bar>
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@ CHECK-NEXT: 6: ldr r3, [pc, #0] @ 0x8 <bar>
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.balign 4
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bar:
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@ CHECK: 00000008 <bar>:
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.word 0x01020304
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@ -0,0 +1,116 @@
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@@ Check that PC-relative memory addressing is annotated
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@ RUN: llvm-mc %s -triple=thumbv7 -filetype=obj | \
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@ RUN: llvm-objdump -d --no-show-raw-insn --triple=thumbv7 - | \
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@ RUN: FileCheck %s
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.text
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foo:
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@ CHECK: 00000000 <foo>:
|
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.word 0x01020304
|
||||
|
||||
_start:
|
||||
@ CHECK: 00000004 <_start>:
|
||||
|
||||
@@ Check a special case immediate for AddrModeT2_pc
|
||||
.balign 4
|
||||
ldr r0, [pc, #-0]
|
||||
@ CHECK: 4: ldr.w r0, [pc, #-0] @ 0x8 <_start+0x4>
|
||||
|
||||
@@ Same instruction, but the address is not 4-byte aligned
|
||||
nop
|
||||
ldr r0, [pc, #-0]
|
||||
@ CHECK: a: ldr.w r0, [pc, #-0] @ 0xc <_start+0x8>
|
||||
|
||||
@@ Check a special case immediate for AddrModeT2_i8s4
|
||||
.balign 4
|
||||
ldrd r0, r1, [pc, #-0]
|
||||
@ CHECK: 10: ldrd r0, r1, [pc, #-0] @ 0x14 <_start+0x10>
|
||||
|
||||
@@ Same instruction, but the address is not 4-byte aligned
|
||||
nop
|
||||
ldrd r0, r1, [pc, #-0]
|
||||
@ CHECK: 16: ldrd r0, r1, [pc, #-0] @ 0x18 <_start+0x14>
|
||||
|
||||
@@ Check AddrModeT2_pc instructions, with positive and negative immediates
|
||||
.balign 4
|
||||
ldr r0, foo
|
||||
ldrb r0, bar
|
||||
ldrsb r0, foo
|
||||
ldrsh r0, bar
|
||||
pli _start
|
||||
pld bar
|
||||
@ CHECK: 1c: ldr.w r0, [pc, #-32] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 20: ldrb.w r0, [pc, #112] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 24: ldrsb.w r0, [pc, #-40] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 28: ldrsh.w r0, [pc, #104] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 2c: pli [pc, #-44] @ 0x4 <_start>
|
||||
@ CHECK-NEXT: 30: pld [pc, #96] @ 0x94 <bar>
|
||||
|
||||
@@ Same instructions, but the addresses are not 4-byte aligned
|
||||
nop
|
||||
ldr r0, foo
|
||||
ldrb r0, bar
|
||||
ldrsb r0, foo
|
||||
ldrsh r0, bar
|
||||
pli _start
|
||||
pld bar
|
||||
@ CHECK: 36: ldr.w r0, [pc, #-56] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 3a: ldrb.w r0, [pc, #88] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 3e: ldrsb.w r0, [pc, #-64] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 42: ldrsh.w r0, [pc, #80] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 46: pli [pc, #-68] @ 0x4 <_start>
|
||||
@ CHECK-NEXT: 4a: pld [pc, #72] @ 0x94 <bar>
|
||||
|
||||
@@ Check AddrModeT2_i8s4 instructions, with positive and negative immediates
|
||||
.balign 4
|
||||
ldrd r0, r1, foo
|
||||
ldrd r0, r1, bar
|
||||
@ CHECK: 50: ldrd r0, r1, [pc, #-84] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 54: ldrd r0, r1, [pc, #60] @ 0x94 <bar>
|
||||
|
||||
@@ Same instructions, but the addresses are not 4-byte aligned
|
||||
nop
|
||||
ldrd r0, r1, foo
|
||||
ldrd r0, r1, bar
|
||||
@ CHECK: 5a: ldrd r0, r1, [pc, #-92] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 5e: ldrd r0, r1, [pc, #52] @ 0x94 <bar>
|
||||
|
||||
@@ Check that AddrModeT2_i8s4 instructions that do not use PC-relative
|
||||
@@ addressingare not annotated
|
||||
ldrd r0, r1, [r2, #8]
|
||||
@ CHECK: 62: ldrd r0, r1, [r2, #8]{{$}}
|
||||
|
||||
@@ Check AddrMode5 instructions, with positive and negative immediates
|
||||
.balign 4
|
||||
ldc p14, c5, foo
|
||||
ldcl p6, c4, bar
|
||||
ldc2 p5, c2, foo
|
||||
ldc2l p3, c1, bar
|
||||
@ CHECK: 68: ldc p14, c5, [pc, #-108] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 6c: ldcl p6, c4, [pc, #36] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 70: ldc2 p5, c2, [pc, #-116] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 74: ldc2l p3, c1, [pc, #28] @ 0x94 <bar>
|
||||
|
||||
@@ Same instructions, but the addresses are not 4-byte aligned
|
||||
nop
|
||||
ldc p14, c5, foo
|
||||
ldcl p6, c4, bar
|
||||
ldc2 p5, c2, foo
|
||||
ldc2l p3, c1, bar
|
||||
@ CHECK: 7a: ldc p14, c5, [pc, #-124] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 7e: ldcl p6, c4, [pc, #20] @ 0x94 <bar>
|
||||
@ CHECK-NEXT: 82: ldc2 p5, c2, [pc, #-132] @ 0x0 <foo>
|
||||
@ CHECK-NEXT: 86: ldc2l p3, c1, [pc, #12] @ 0x94 <bar>
|
||||
|
||||
@@ Check that AddrMode5 instruction that do not use PC+imm addressing are not
|
||||
@@ annotated
|
||||
ldc p14, c5, [r1, #8]
|
||||
ldc p14, c5, [pc], {16}
|
||||
@ CHECK: 8a: ldc p14, c5, [r1, #8]{{$}}
|
||||
@ CHECK-NEXT: 8e: ldc p14, c5, [pc], {16}{{$}}
|
||||
|
||||
.balign 4
|
||||
bar:
|
||||
@ CHECK: 00000094 <bar>:
|
||||
.word 0x01020304
|
||||
Loading…
Reference in New Issue