forked from OSchip/llvm-project
parent
3cb9ff8863
commit
dd905b0e9b
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@ -2924,11 +2924,6 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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Op.getOperand(1), Op.getOperand(2));
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return DAG.getNode(ISD::BITCAST, DL, VT, Node);
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}
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case AMDGPUIntrinsic::SI_packf16: { // Legacy name
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EVT VT = Op.getValueType();
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return DAG.getNode(AMDGPUISD::CVT_PKRTZ_F16_F32, DL, VT,
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Op.getOperand(1), Op.getOperand(2));
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}
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default:
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return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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}
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@ -14,8 +14,6 @@
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let TargetPrefix = "SI", isTarget = 1 in {
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def int_SI_packf16 : Intrinsic <[llvm_i32_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
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def int_SI_export : Intrinsic <[],
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[llvm_i32_ty, // en
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llvm_i32_ty, // vm (FIXME: should be i1)
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@ -1,28 +0,0 @@
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; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}main:
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; GCN: v_cvt_pkrtz_f16_f32
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; GCN: v_cvt_pkrtz_f16_f32
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; GCN-NOT: v_cvt_pkrtz_f16_f32
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define amdgpu_ps void @main(float %src) {
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main_body:
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%p1 = call i32 @llvm.SI.packf16(float undef, float %src)
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%p2 = call i32 @llvm.SI.packf16(float %src, float undef)
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%p3 = call i32 @llvm.SI.packf16(float undef, float undef)
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%f1 = bitcast i32 %p1 to float
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%f2 = bitcast i32 %p2 to float
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%f3 = bitcast i32 %p3 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 1, float undef, float %f1, float undef, float %f1)
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call void @llvm.SI.export(i32 15, i32 1, i32 0, i32 0, i32 1, float undef, float %f2, float undef, float %f2)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float undef, float %f3, float undef, float %f2)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #0
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind readnone }
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