From dd7e407d81081b06bc792bc436adfcb583ed9902 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Thu, 2 Jun 2022 14:59:27 -0400 Subject: [PATCH] AMDGPU: Move SpilledReg from MFI to SIRegisterInfo This isn't the most natural place for it, but it avoids a circular include dependency in an out of tree patch. --- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 4 ++-- .../Target/AMDGPU/SIMachineFunctionInfo.cpp | 4 ++-- .../lib/Target/AMDGPU/SIMachineFunctionInfo.h | 21 ++++++------------- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 10 ++++----- llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 11 ++++++++++ 5 files changed, 25 insertions(+), 25 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp index 4e4b06ae3aa0..a57e81eb4e4a 100644 --- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp @@ -828,7 +828,7 @@ void SIFrameLowering::emitPrologue(MachineFunction &MF, assert(!MFI.isDeadObjectIndex(FI)); assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill); - ArrayRef Spill = + ArrayRef Spill = FuncInfo->getSGPRToVGPRSpills(FI); assert(Spill.size() == 1); @@ -1017,7 +1017,7 @@ void SIFrameLowering::emitEpilogue(MachineFunction &MF, auto RestoreSGPRFromVGPRLane = [&](Register Reg, const int FI) { assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill); - ArrayRef Spill = + ArrayRef Spill = FuncInfo->getSGPRToVGPRSpills(FI); assert(Spill.size() == 1); BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::V_READLANE_B32), Reg) diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 33118bf5b743..d0772602a98d 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -275,7 +275,7 @@ bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF, /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI. bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF, int FI) { - std::vector &SpillLanes = SGPRToVGPRSpills[FI]; + std::vector &SpillLanes = SGPRToVGPRSpills[FI]; // This has already been allocated. if (!SpillLanes.empty()) @@ -338,7 +338,7 @@ bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF, LaneVGPR = SpillVGPRs.back().VGPR; } - SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); + SpillLanes.push_back(SIRegisterInfo::SpilledReg(LaneVGPR, VGPRIndex)); } return true; diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 19725c012005..19338596e3b0 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -452,17 +452,6 @@ private: MCPhysReg getNextSystemSGPR() const; public: - struct SpilledReg { - Register VGPR; - int Lane = -1; - - SpilledReg() = default; - SpilledReg(Register R, int L) : VGPR (R), Lane (L) {} - - bool hasLane() { return Lane != -1;} - bool hasReg() { return VGPR != 0;} - }; - struct SGPRSpillVGPR { // VGPR used for SGPR spills Register VGPR; @@ -501,7 +490,7 @@ public: private: // Track VGPR + wave index for each subregister of the SGPR spilled to // frameindex key. - DenseMap> SGPRToVGPRSpills; + DenseMap> SGPRToVGPRSpills; unsigned NumVGPRSpillLanes = 0; SmallVector SpillVGPRs; @@ -554,10 +543,12 @@ public: WWMReservedRegs.insert(Reg); } - ArrayRef getSGPRToVGPRSpills(int FrameIndex) const { + ArrayRef + getSGPRToVGPRSpills(int FrameIndex) const { auto I = SGPRToVGPRSpills.find(FrameIndex); - return (I == SGPRToVGPRSpills.end()) ? - ArrayRef() : makeArrayRef(I->second); + return (I == SGPRToVGPRSpills.end()) + ? ArrayRef() + : makeArrayRef(I->second); } ArrayRef getSGPRSpillVGPRs() const { return SpillVGPRs; } diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index 330357798103..39f6ce180bd3 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -1673,8 +1673,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, bool OnlyToVGPR) const { SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); - ArrayRef VGPRSpills = - SB.MFI.getSGPRToVGPRSpills(Index); + ArrayRef VGPRSpills = SB.MFI.getSGPRToVGPRSpills(Index); bool SpillToVGPR = !VGPRSpills.empty(); if (OnlyToVGPR && !SpillToVGPR) return false; @@ -1692,7 +1691,7 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI, SB.NumSubRegs == 1 ? SB.SuperReg : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); - SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; + SpilledReg Spill = VGPRSpills[i]; bool UseKill = SB.IsKill && i == SB.NumSubRegs - 1; @@ -1793,8 +1792,7 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, bool OnlyToVGPR) const { SGPRSpillBuilder SB(*this, *ST.getInstrInfo(), isWave32, MI, Index, RS); - ArrayRef VGPRSpills = - SB.MFI.getSGPRToVGPRSpills(Index); + ArrayRef VGPRSpills = SB.MFI.getSGPRToVGPRSpills(Index); bool SpillToVGPR = !VGPRSpills.empty(); if (OnlyToVGPR && !SpillToVGPR) return false; @@ -1806,7 +1804,7 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI, ? SB.SuperReg : Register(getSubReg(SB.SuperReg, SB.SplitParts[i])); - SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i]; + SpilledReg Spill = VGPRSpills[i]; auto MIB = BuildMI(*SB.MBB, MI, SB.DL, SB.TII.get(AMDGPU::V_READLANE_B32), SubReg) .addReg(Spill.VGPR) diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h index 2f3b489a4932..9bfbc253410b 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h @@ -51,6 +51,17 @@ private: public: SIRegisterInfo(const GCNSubtarget &ST); + struct SpilledReg { + Register VGPR; + int Lane = -1; + + SpilledReg() = default; + SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} + + bool hasLane() { return Lane != -1; } + bool hasReg() { return VGPR != 0; } + }; + /// \returns the sub reg enum value for the given \p Channel /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0) static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);