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Fix spelling mistake in comments. NFCI. 

llvm-svn: 337442
This commit is contained in:
Simon Pilgrim 2018-07-19 09:14:39 +00:00
parent e0099f1c6d
commit dd7bf598cc
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/X86/X86InstrSSE.td
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@ -724,7 +724,7 @@ let Predicates = [UseSSE1] in {
(MOVLPSmr addr:$src1, VR128:$src2)>; (MOVLPSmr addr:$src1, VR128:$src2)>;
// This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll // This pattern helps select MOVLPS on SSE1 only targets. With SSE2 we'll
// end up with a movsd or bleand instead of shufp. // end up with a movsd or blend instead of shufp.
// No need for aligned load, we're only loading 64-bits. // No need for aligned load, we're only loading 64-bits.
def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)), def : Pat<(X86Shufp (loadv4f32 addr:$src2), VR128:$src1, (i8 -28)),
(MOVLPSrm VR128:$src1, addr:$src2)>; (MOVLPSrm VR128:$src1, addr:$src2)>;
@ -780,7 +780,7 @@ let Predicates = [UseAVX] in {
let Predicates = [UseSSE1] in { let Predicates = [UseSSE1] in {
// This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll // This pattern helps select MOVHPS on SSE1 only targets. With SSE2 we'll
// end up with a movsd or bleand instead of shufp. // end up with a movsd or blend instead of shufp.
// No need for aligned load, we're only loading 64-bits. // No need for aligned load, we're only loading 64-bits.
def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)), def : Pat<(X86Movlhps VR128:$src1, (loadv4f32 addr:$src2)),
(MOVHPSrm VR128:$src1, addr:$src2)>; (MOVHPSrm VR128:$src1, addr:$src2)>;