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[X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar i8 or i16 and need to zero extend it, make sure we use a vXi32 type of the full vector width. 

Previously, this was hardcoded to v4i32, but if the input type is 256 bits we need to use v8i32.

Fixes PR35443

llvm-svn: 319208
This commit is contained in:
Craig Topper 2017-11-28 19:25:45 +00:00
parent 3aa8eaa951
commit dd4295626b
2 changed files with 31 additions and 1 deletions
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2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -10149,7 +10149,7 @@ static SDValue lowerVectorShuffleAsElementInsertion(
return SDValue();
// Zero-extend directly to i32.
ExtVT = MVT::v4i32;
ExtVT = MVT::getVectorVT(MVT::i32, ExtVT.getSizeInBits() / 32);
V2S = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, V2S);
}
V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, ExtVT, V2S);

30
llvm/test/CodeGen/X86/pr35443.ll Normal file
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@ -0,0 +1,30 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=skx | FileCheck %s
@ac = external local_unnamed_addr global [20 x i8], align 16
@ai3 = external local_unnamed_addr global [20 x i32], align 16
; Function Attrs: norecurse nounwind uwtable
define void @main() {
; CHECK-LABEL: main:
; CHECK: # BB#0: # %entry
; CHECK-NEXT: movzbl ac+{{.*}}(%rip), %eax
; CHECK-NEXT: vmovd %eax, %xmm0
; CHECK-NEXT: vpxor %xmm1, %xmm1, %xmm1
; CHECK-NEXT: vpsubq %ymm0, %ymm1, %ymm0
; CHECK-NEXT: vpmovqd %ymm0, ai3+{{.*}}(%rip)
; CHECK-NEXT: vzeroupper
; CHECK-NEXT: retq
entry:
%wide.masked.load66 = call <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>* bitcast (i8* getelementptr inbounds ([20 x i8], [20 x i8]* @ac, i64 0, i64 4) to <4 x i8>*), i32 1, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i8> undef)
%0 = zext <4 x i8> %wide.masked.load66 to <4 x i64>
%1 = sub <4 x i64> zeroinitializer, %0
%predphi = shufflevector <4 x i64> %1, <4 x i64> undef, <4 x i32> <i32 0, i32 5, i32 6, i32 7>
%2 = trunc <4 x i64> %predphi to <4 x i32>
%3 = add <4 x i32> zeroinitializer, %2
store <4 x i32> %3, <4 x i32>* bitcast (i32* getelementptr inbounds ([20 x i32], [20 x i32]* @ai3, i64 0, i64 4) to <4 x i32>*), align 16
ret void
}
; Function Attrs: argmemonly nounwind readonly
declare <4 x i8> @llvm.masked.load.v4i8.p0v4i8(<4 x i8>*, i32, <4 x i1>, <4 x i8>)