forked from OSchip/llvm-project
AMDGPU: Cleanup / relax tests for future changes
llvm-svn: 347576
This commit is contained in:
Matt Arsenault
parent
b795ed9381
commit
dcdf3ddff5
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@ -48,8 +48,8 @@ entry:
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; GCN: v_readlane_b32
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; GCN-NOT: v_readlane_b32 s32
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; GCN: buffer_load_dword v32,
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; GCN: buffer_load_dword v33,
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; GCN-DAG: buffer_load_dword v32,
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; GCN-DAG: buffer_load_dword v33,
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; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
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; GCN: s_setpc_b64
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define void @void_func_byval_struct_non_leaf(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 {
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@ -75,23 +75,22 @@
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name: sgpr_spill_wrong_stack_id
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tracksRegLiveness: true
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frameInfo:
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adjustsStack: false
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hasCalls: true
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body: |
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bb.0.bb:
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%8:sreg_32_xm0 = COPY $sgpr5
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%4:vreg_64 = IMPLICIT_DEF
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%3:vgpr_32 = FLAT_LOAD_DWORD %4, 0, 0, 0, implicit $exec, implicit $flat_scr
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%5:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
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bb.0:
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%0:sreg_32_xm0 = COPY $sgpr5
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%1:vreg_64 = IMPLICIT_DEF
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%2:vgpr_32 = FLAT_LOAD_DWORD %1, 0, 0, 0, implicit $exec, implicit $flat_scr
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%3:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-rel32-lo) @func + 4, target-flags(amdgpu-rel32-hi) @func + 4, implicit-def dead $scc
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ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
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$sgpr5 = COPY %8
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%12:sreg_32_xm0 = COPY $sgpr5
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dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit undef $vgpr0
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$sgpr5 = COPY %0
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%4:sreg_32_xm0 = COPY $sgpr5
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ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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ADJCALLSTACKUP 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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$vgpr0 = COPY %3
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dead $sgpr30_sgpr31 = SI_CALL %5, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0
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$sgpr5 = COPY %12
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$vgpr0 = COPY %2
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dead $sgpr30_sgpr31 = SI_CALL %3, @func, csr_amdgpu_highregs, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0
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$sgpr5 = COPY %4
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ADJCALLSTACKDOWN 0, 0, implicit-def $sgpr32, implicit $sgpr32, implicit $sgpr5
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...
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@ -1,4 +1,4 @@
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# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
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# https://bugs.llvm.org/show_bug.cgi?id=33620
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---
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@ -10,7 +10,7 @@
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# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $exec
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# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
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# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
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# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec
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# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $exec
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# CHECK: S_NOP 0, implicit %6.sub1
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# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr5, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
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@ -19,20 +19,16 @@
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name: expecting_non_empty_interval
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_64, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vgpr_32, preferred-register: '' }
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- { id: 3, class: vreg_64, preferred-register: '' }
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub1 = V_MAC_F32_e32 0, undef %1, undef %0.sub1, implicit $exec
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undef %3.sub1 = V_MOV_B32_e32 1786773504, implicit $exec
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dead %2 = V_MUL_F32_e32 0, %3.sub1, implicit $exec
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undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $exec
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undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
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dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $exec
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bb.1:
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S_NOP 0, implicit %3.sub1
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S_NOP 0, implicit %2.sub1
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S_NOP 0, implicit %0.sub1
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S_NOP 0, implicit undef %0.sub0
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@ -44,29 +40,24 @@ body: |
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# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
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# CHECK-NOT: MOV
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# CHECK: undef %3.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
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# CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
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# CHECK: bb.1:
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# CHECK-NEXT: S_NOP 0, implicit %3.sub2
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# CHECK-NEXT: S_NOP 0, implicit undef %6.sub0
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# CHECK-NEXT: undef %4.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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# CHECK-NEXT: S_NOP 0, implicit %4.sub2
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# CHECK-NEXT: S_NOP 0, implicit %1.sub2
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# CHECK-NEXT: S_NOP 0, implicit undef %4.sub0
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# CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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# CHECK-NEXT: S_NOP 0, implicit %2.sub2
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name: rematerialize_empty_interval_has_reference
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vreg_128, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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- { id: 2, class: vgpr_32, preferred-register: '' }
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- { id: 3, class: vreg_128, preferred-register: '' }
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub2 = V_MOV_B32_e32 0, implicit $exec
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undef %3.sub2 = V_MOV_B32_e32 1786773504, implicit $exec
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undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
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bb.1:
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S_NOP 0, implicit %3.sub2
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S_NOP 0, implicit %1.sub2
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S_NOP 0, implicit undef %0.sub0
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S_NOP 0, implicit %0.sub2
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@ -17,18 +17,12 @@
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name: no_merge_sgpr_vgpr_spill_slot
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: sreg_32_xm0_xexec }
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- { id: 2, class: vgpr_32 }
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- { id: 3, class: sreg_32_xm0_xexec }
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body: |
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bb.0:
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%0 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
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%2 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
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%0:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
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%2:vgpr_32 = FLAT_LOAD_DWORD undef $vgpr0_vgpr1, 0, 0, 0, implicit $flat_scr, implicit $exec
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S_NOP 0, implicit %0
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%1 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
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%3 = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
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%1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
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%3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM undef $sgpr0_sgpr1, 0, 0
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S_NOP 0, implicit %1
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...
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