forked from OSchip/llvm-project
- Add getOperandConstraint() to TargetInstrDescriptor.
- convertToThreeAddress() change to allow single two-address MI to be converted into one or more 3-address MIs. llvm-svn: 32094
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@ -15,6 +15,7 @@
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/DataTypes.h"
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#include <vector>
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#include <vector>
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#include <cassert>
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#include <cassert>
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@ -30,6 +31,7 @@ class Constant;
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class Function;
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class Function;
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class MachineCodeForInstruction;
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class MachineCodeForInstruction;
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class TargetRegisterClass;
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class TargetRegisterClass;
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class LiveVariables;
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//---------------------------------------------------------------------------
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//---------------------------------------------------------------------------
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// Data types used to define information about a single machine instruction
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// Data types used to define information about a single machine instruction
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@ -91,6 +93,12 @@ const unsigned M_LOOK_UP_PTR_REG_CLASS = 1 << 0;
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/// operand that controls an M_PREDICATED instruction.
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/// operand that controls an M_PREDICATED instruction.
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const unsigned M_PREDICATE_OPERAND = 1 << 1;
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const unsigned M_PREDICATE_OPERAND = 1 << 1;
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namespace TOI {
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// Operand constraints: only "tied_to" for now.
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enum OperandConstraint {
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TIED_TO = 0 // Must be allocated the same register as.
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};
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}
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/// TargetOperandInfo - This holds information about one operand of a machine
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/// TargetOperandInfo - This holds information about one operand of a machine
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/// instruction, indicating the register class for register operands, etc.
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/// instruction, indicating the register class for register operands, etc.
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@ -119,6 +127,18 @@ public:
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitUses; // Registers implicitly read by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const unsigned *ImplicitDefs; // Registers implicitly defined by this instr
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const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
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const TargetOperandInfo *OpInfo; // 'numOperands' entries about operands.
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(unsigned OpNum,
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TOI::OperandConstraint Constraint) const {
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assert(OpNum < numOperands && "Invalid operand # of TargetInstrInfo");
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if (OpInfo[OpNum].Constraints & (1 << Constraint)) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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};
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};
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@ -230,22 +250,11 @@ public:
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return get(Opcode).Flags & M_VARIABLE_OPS;
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return get(Opcode).Flags & M_VARIABLE_OPS;
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}
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}
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// Operand constraints: only "tied_to" for now.
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enum OperandConstraint {
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TIED_TO = 0 // Must be allocated the same register as.
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};
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// getOperandConstraint - Returns the value of the specific constraint if
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/// it is set. Returns -1 if it is not set.
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/// it is set. Returns -1 if it is not set.
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int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
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int getOperandConstraint(MachineOpCode Opcode, unsigned OpNum,
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OperandConstraint Constraint) const {
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TOI::OperandConstraint Constraint) const {
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assert(OpNum < get(Opcode).numOperands &&
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return get(Opcode).getOperandConstraint(OpNum, Constraint);
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"Invalid operand # of TargetInstrInfo");
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if (get(Opcode).OpInfo[OpNum].Constraints & (1 << Constraint)) {
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unsigned Pos = 16 + Constraint * 4;
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return (int)(get(Opcode).OpInfo[OpNum].Constraints >> Pos) & 0xf;
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}
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return -1;
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}
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}
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/// findTiedToSrcOperand - Returns the operand that is tied to the specified
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/// findTiedToSrcOperand - Returns the operand that is tied to the specified
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@ -287,15 +296,17 @@ public:
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/// convertToThreeAddress - This method must be implemented by targets that
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// may be able to convert a two-address instruction into one or moretrue
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/// three-address instruction on demand. This allows the X86 target (for
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/// three-address instructions on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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/// would require register copies due to two-addressness.
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///
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///
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/// This method returns a null pointer if the transformation cannot be
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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/// performed, otherwise it returns the last new instruction.
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///
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///
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virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const {
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
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return 0;
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return 0;
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}
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}
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