diff --git a/clang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def b/clang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def index 93f560fc5adc..389eadb21d01 100644 --- a/clang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def +++ b/clang/include/clang/Basic/BuiltinsHexagonMapCustomDep.def @@ -8,199 +8,7 @@ // Automatically generated file, do not edit! //===----------------------------------------------------------------------===// -CUSTOM_BUILTIN_MAPPING(A2_add, 0) -CUSTOM_BUILTIN_MAPPING(A2_addi, 0) -CUSTOM_BUILTIN_MAPPING(A2_addp, 0) -CUSTOM_BUILTIN_MAPPING(A2_and, 0) -CUSTOM_BUILTIN_MAPPING(A2_andir, 0) -CUSTOM_BUILTIN_MAPPING(A2_neg, 0) -CUSTOM_BUILTIN_MAPPING(A2_not, 0) -CUSTOM_BUILTIN_MAPPING(A2_or, 0) -CUSTOM_BUILTIN_MAPPING(A2_orir, 0) -CUSTOM_BUILTIN_MAPPING(A2_sub, 0) -CUSTOM_BUILTIN_MAPPING(A2_subp, 0) -CUSTOM_BUILTIN_MAPPING(A2_subri, 0) -CUSTOM_BUILTIN_MAPPING(A2_sxtb, 0) -CUSTOM_BUILTIN_MAPPING(A2_sxth, 0) -CUSTOM_BUILTIN_MAPPING(A2_xor, 0) -CUSTOM_BUILTIN_MAPPING(A2_zxtb, 0) -CUSTOM_BUILTIN_MAPPING(A2_zxth, 0) -CUSTOM_BUILTIN_MAPPING(M2_dpmpyss_s0, 0) -CUSTOM_BUILTIN_MAPPING(M2_dpmpyuu_s0, 0) -CUSTOM_BUILTIN_MAPPING(M2_mpyi, 0) -CUSTOM_BUILTIN_MAPPING(M2_mpysmi, 0) -CUSTOM_BUILTIN_MAPPING(M2_mpyui, 0) -CUSTOM_BUILTIN_MAPPING(S2_asl_i_p, 0) -CUSTOM_BUILTIN_MAPPING(S2_asl_i_r, 0) -CUSTOM_BUILTIN_MAPPING(S2_asr_i_p, 0) -CUSTOM_BUILTIN_MAPPING(S2_asr_i_r, 0) -CUSTOM_BUILTIN_MAPPING(S2_lsr_i_p, 0) -CUSTOM_BUILTIN_MAPPING(S2_lsr_i_r, 0) -CUSTOM_BUILTIN_MAPPING(V6_pred_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_and_n, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_and_n_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_not, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_not_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_or_n, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_or_n_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_scalar2, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_scalar2_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nqpred_ai, 64) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nqpred_ai_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_nqpred_ai, 64) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_nqpred_ai_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_qpred_ai, 64) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_nt_qpred_ai_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_qpred_ai, 64) -CUSTOM_BUILTIN_MAPPING(V6_vS32b_qpred_ai_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddbnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddbnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddbq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddbq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddhnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddhnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddhq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddhq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddwnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddwnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandqrt, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandqrt_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandqrt_acc, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandqrt_acc_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandvrt, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandvrt_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandvrt_acc, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandvrt_acc_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqb, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqb_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqb_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqb_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqb_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqb_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqb_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqb_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqh, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqh_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqh_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqh_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqh_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqh_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqh_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqh_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqw, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqw_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqw_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqw_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqw_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqw_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_veqw_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_veqw_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtb, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtb_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgth, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgth_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgth_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgth_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgth_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgth_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgth_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgth_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtub, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtub_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuh_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtuw_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtw, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_and, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_and_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_or, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_or_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_xor, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgtw_xor_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vmux, 64) -CUSTOM_BUILTIN_MAPPING(V6_vmux_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubbnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubbnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubbq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubbq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubhnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubhnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubhq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubhq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubwnq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubwnq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vsubwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vsubwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vswap, 64) -CUSTOM_BUILTIN_MAPPING(V6_vswap_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_pred_scalar2v2, 64) -CUSTOM_BUILTIN_MAPPING(V6_pred_scalar2v2_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_shuffeqh, 64) -CUSTOM_BUILTIN_MAPPING(V6_shuffeqh_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_shuffeqw, 64) -CUSTOM_BUILTIN_MAPPING(V6_shuffeqw_128B, 128) CUSTOM_BUILTIN_MAPPING(V6_vaddcarry, 64) CUSTOM_BUILTIN_MAPPING(V6_vaddcarry_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandnqrt, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandnqrt_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandnqrt_acc, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandnqrt_acc_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandvnqv, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandvnqv_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vandvqv, 64) -CUSTOM_BUILTIN_MAPPING(V6_vandvqv_128B, 128) CUSTOM_BUILTIN_MAPPING(V6_vsubcarry, 64) CUSTOM_BUILTIN_MAPPING(V6_vsubcarry_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgathermhq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgathermhq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgathermhwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgathermhwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vgathermwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vgathermwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqb, 64) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqb_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqh, 64) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqh_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqw, 64) -CUSTOM_BUILTIN_MAPPING(V6_vprefixqw_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vscattermhq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vscattermhq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vscattermhwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vscattermhwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vscattermwq, 64) -CUSTOM_BUILTIN_MAPPING(V6_vscattermwq_128B, 128) -CUSTOM_BUILTIN_MAPPING(V6_vaddcarrysat, 64) -CUSTOM_BUILTIN_MAPPING(V6_vaddcarrysat_128B, 128) diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 7224b10f2e90..1982b40ff667 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -18596,6 +18596,7 @@ getIntrinsicForHexagonNonGCCBuiltin(unsigned BuiltinID) { CUSTOM_BUILTIN_MAPPING(S2_storerf_pcr, 0) CUSTOM_BUILTIN_MAPPING(S2_storeri_pcr, 0) CUSTOM_BUILTIN_MAPPING(S2_storerd_pcr, 0) + // Legacy builtins that take a vector in place of a vector predicate. CUSTOM_BUILTIN_MAPPING(V6_vmaskedstoreq, 64) CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorenq, 64) CUSTOM_BUILTIN_MAPPING(V6_vmaskedstorentq, 64) @@ -18733,6 +18734,27 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return Builder.CreateExtractValue(Result, 0); } + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstoreq: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorenq: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentq: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentnq: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstoreq_128B: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorenq_128B: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentq_128B: + case Hexagon::BI__builtin_HEXAGON_V6_vmaskedstorentnq_128B: { + SmallVector Ops; + const Expr *PredOp = E->getArg(0); + // There will be an implicit cast to a boolean vector. Strip it. + if (auto *Cast = dyn_cast(PredOp)) { + if (Cast->getCastKind() == CK_BitCast) + PredOp = Cast->getSubExpr(); + Ops.push_back(V2Q(EmitScalarExpr(PredOp))); + } + for (int i = 1, e = E->getNumArgs(); i != e; ++i) + Ops.push_back(EmitScalarExpr(E->getArg(i))); + return Builder.CreateCall(CGM.getIntrinsic(ID), Ops); + } + case Hexagon::BI__builtin_HEXAGON_L2_loadrub_pci: case Hexagon::BI__builtin_HEXAGON_L2_loadrb_pci: case Hexagon::BI__builtin_HEXAGON_L2_loadruh_pci: @@ -18769,40 +18791,6 @@ Value *CodeGenFunction::EmitHexagonBuiltinExpr(unsigned BuiltinID, return MakeBrevLd(Intrinsic::hexagon_L2_loadri_pbr, Int32Ty); case Hexagon::BI__builtin_brev_ldd: return MakeBrevLd(Intrinsic::hexagon_L2_loadrd_pbr, Int64Ty); - - default: { - if (ID == Intrinsic::not_intrinsic) - return nullptr; - - auto IsVectorPredTy = [](llvm::Type *T) { - return T->isVectorTy() && - cast(T)->getElementType()->isIntegerTy(1); - }; - - llvm::Function *IntrFn = CGM.getIntrinsic(ID); - llvm::FunctionType *IntrTy = IntrFn->getFunctionType(); - SmallVector Ops; - for (unsigned i = 0, e = IntrTy->getNumParams(); i != e; ++i) { - llvm::Type *T = IntrTy->getParamType(i); - const Expr *A = E->getArg(i); - if (IsVectorPredTy(T)) { - // There will be an implicit cast to a boolean vector. Strip it. - if (auto *Cast = dyn_cast(A)) { - if (Cast->getCastKind() == CK_BitCast) - A = Cast->getSubExpr(); - } - Ops.push_back(V2Q(EmitScalarExpr(A))); - } else { - Ops.push_back(EmitScalarExpr(A)); - } - } - - llvm::Value *Call = Builder.CreateCall(IntrFn, Ops); - if (IsVectorPredTy(IntrTy->getReturnType())) - Call = Q2V(Call); - - return Call; - } // default } // switch return nullptr; diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h index 41ce7a6b93e9..dab19949b889 100644 --- a/clang/lib/Headers/hvx_hexagon_protos.h +++ b/clang/lib/Headers/hvx_hexagon_protos.h @@ -9,7 +9,6 @@ //===----------------------------------------------------------------------===// - #ifndef _HVX_HEXAGON_PROTOS_H_ #define _HVX_HEXAGON_PROTOS_H_ 1 @@ -28,7 +27,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_R_vextract_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw) +#define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -39,7 +38,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_hi_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi) +#define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -50,7 +49,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_lo_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo) +#define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -61,7 +60,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_V_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw) +#define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -72,7 +71,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_and_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and) +#define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -83,7 +82,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_and_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n) +#define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -94,7 +93,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_not_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not) +#define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -105,7 +104,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_or_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or) +#define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -116,7 +115,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_or_QQn __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n) +#define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -127,7 +126,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vsetq_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2) +#define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -138,7 +137,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_xor_QQ __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor) +#define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -149,7 +148,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vmem_QnRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai) +#define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -160,7 +159,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vmem_QnRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai) +#define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -171,7 +170,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vmem_QRIV_nt __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai) +#define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -182,7 +181,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vmem_QRIV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai) +#define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -193,7 +192,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuh_vabsdiff_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh) +#define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -204,7 +203,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vub_vabsdiff_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub) +#define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -215,7 +214,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuh_vabsdiff_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh) +#define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -226,7 +225,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vabsdiff_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw) +#define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -237,7 +236,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vabs_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh) +#define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -248,7 +247,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vabs_Vh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat) +#define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -259,7 +258,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vabs_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw) +#define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -270,7 +269,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vabs_Vw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat) +#define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -281,7 +280,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vadd_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb) +#define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -292,7 +291,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wb_vadd_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv) +#define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -303,7 +302,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_condacc_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq) +#define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -314,7 +313,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_condacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq) +#define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -325,7 +324,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh) +#define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -336,7 +335,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vadd_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv) +#define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -347,7 +346,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_condacc_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq) +#define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -358,7 +357,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_condacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq) +#define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -369,7 +368,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vadd_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat) +#define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -380,7 +379,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vadd_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv) +#define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -391,7 +390,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vadd_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw) +#define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -402,7 +401,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vadd_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh) +#define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -413,7 +412,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vadd_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat) +#define Q6_Vub_vadd_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -424,7 +423,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wub_vadd_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv) +#define Q6_Wub_vadd_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -435,7 +434,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vadd_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat) +#define Q6_Vuh_vadd_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -446,7 +445,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuh_vadd_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv) +#define Q6_Wuh_vadd_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -457,7 +456,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vadd_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw) +#define Q6_Ww_vadd_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -468,7 +467,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vadd_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw) +#define Q6_Vw_vadd_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -479,7 +478,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vadd_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv) +#define Q6_Ww_vadd_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddw_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -490,7 +489,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_condacc_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq) +#define Q6_Vw_condacc_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -501,7 +500,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_condacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq) +#define Q6_Vw_condacc_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -512,7 +511,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vadd_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat) +#define Q6_Vw_vadd_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -523,7 +522,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vadd_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv) +#define Q6_Ww_vadd_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddwsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -534,7 +533,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_valign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb) +#define Q6_V_valign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignb)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -545,7 +544,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_valign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi) +#define Q6_V_valign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_valignbi)(Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -556,7 +555,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vand_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand) +#define Q6_V_vand_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vand)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -567,7 +566,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_V_vand_QR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt) +#define Q6_V_vand_QR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -578,7 +577,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_V_vandor_VQR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc) +#define Q6_V_vandor_VQR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -589,7 +588,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Q_vand_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt) +#define Q6_Q_vand_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)(Vu,Rt)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -600,7 +599,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Q_vandor_QVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc) +#define Q6_Q_vandor_QVR(Qx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt_acc)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Rt)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -611,7 +610,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasl_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh) +#define Q6_Vh_vasl_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -622,7 +621,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasl_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv) +#define Q6_Vh_vasl_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslhv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -633,7 +632,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vasl_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw) +#define Q6_Vw_vasl_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -644,7 +643,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vaslacc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc) +#define Q6_Vw_vaslacc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslw_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -655,7 +654,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vasl_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv) +#define Q6_Vw_vasl_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslwv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -666,7 +665,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasr_VhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh) +#define Q6_Vh_vasr_VhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -677,7 +676,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat) +#define Q6_Vb_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -688,7 +687,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vasr_VhVhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat) +#define Q6_Vub_vasr_VhVhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -699,7 +698,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat) +#define Q6_Vub_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhubsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -710,7 +709,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv) +#define Q6_Vh_vasr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -721,7 +720,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vasr_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw) +#define Q6_Vw_vasr_VwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -732,7 +731,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vasracc_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc) +#define Q6_Vw_vasracc_VwVwR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrw_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -743,7 +742,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasr_VwVwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh) +#define Q6_Vh_vasr_VwVwR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwh)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -754,7 +753,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat) +#define Q6_Vh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -765,7 +764,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat) +#define Q6_Vh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwhsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -776,7 +775,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vasr_VwVwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat) +#define Q6_Vuh_vasr_VwVwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -787,7 +786,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vasr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv) +#define Q6_Vw_vasr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -798,7 +797,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_equals_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign) +#define Q6_V_equals_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassign)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -809,7 +808,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_equals_W __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp) +#define Q6_W_equals_W(Vuu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vassignp)(Vuu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -820,7 +819,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh) +#define Q6_Vh_vavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -831,7 +830,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vavg_VhVh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd) +#define Q6_Vh_vavg_VhVh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavghrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -842,7 +841,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub) +#define Q6_Vub_vavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -853,7 +852,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vavg_VubVub_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd) +#define Q6_Vub_vavg_VubVub_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgubrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -864,7 +863,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vavg_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh) +#define Q6_Vuh_vavg_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -875,7 +874,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vavg_VuhVuh_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd) +#define Q6_Vuh_vavg_VuhVuh_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguhrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -886,7 +885,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw) +#define Q6_Vw_vavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -897,7 +896,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vavg_VwVw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd) +#define Q6_Vw_vavg_VwVw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgwrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -908,7 +907,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vcl0_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h) +#define Q6_Vuh_vcl0_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0h)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -919,7 +918,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vcl0_Vuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w) +#define Q6_Vuw_vcl0_Vuw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcl0w)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -930,7 +929,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_vcombine_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine) +#define Q6_W_vcombine_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vcombine)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -941,7 +940,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0) +#define Q6_V_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vd0)() #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -952,7 +951,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vdeal_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb) +#define Q6_Vb_vdeal_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -963,7 +962,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vdeale_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w) +#define Q6_Vb_vdeale_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealb4w)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -974,7 +973,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vdeal_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh) +#define Q6_Vh_vdeal_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -985,7 +984,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_vdeal_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd) +#define Q6_W_vdeal_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdealvdd)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -996,7 +995,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta) +#define Q6_V_vdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdelta)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1007,7 +1006,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vdmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus) +#define Q6_Vh_vdmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1018,7 +1017,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vdmpyacc_VhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc) +#define Q6_Vh_vdmpyacc_VhVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1029,7 +1028,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vdmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv) +#define Q6_Wh_vdmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1040,7 +1039,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vdmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc) +#define Q6_Wh_vdmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpybus_dv_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1051,7 +1050,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb) +#define Q6_Vw_vdmpy_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1062,7 +1061,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc) +#define Q6_Vw_vdmpyacc_VwVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1073,7 +1072,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vdmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv) +#define Q6_Ww_vdmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1084,7 +1083,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vdmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc) +#define Q6_Ww_vdmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhb_dv_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1095,7 +1094,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_WhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat) +#define Q6_Vw_vdmpy_WhRh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1106,7 +1105,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwWhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc) +#define Q6_Vw_vdmpyacc_VwWhRh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhisat_acc)(Vx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1117,7 +1116,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_VhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat) +#define Q6_Vw_vdmpy_VhRh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1128,7 +1127,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc) +#define Q6_Vw_vdmpyacc_VwVhRh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsat_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1139,7 +1138,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_WhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat) +#define Q6_Vw_vdmpy_WhRuh_sat(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1150,7 +1149,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwWhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc) +#define Q6_Vw_vdmpyacc_VwWhRuh_sat(Vx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsuisat_acc)(Vx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1161,7 +1160,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_VhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat) +#define Q6_Vw_vdmpy_VhRuh_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1172,7 +1171,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwVhRuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc) +#define Q6_Vw_vdmpyacc_VwVhRuh_sat(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhsusat_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1183,7 +1182,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpy_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat) +#define Q6_Vw_vdmpy_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1194,7 +1193,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vdmpyacc_VwVhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc) +#define Q6_Vw_vdmpyacc_VwVhVh_sat(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdmpyhvsat_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1205,7 +1204,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vdsad_WuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh) +#define Q6_Wuw_vdsad_WuhRuh(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1216,7 +1215,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vdsadacc_WuwWuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc) +#define Q6_Wuw_vdsadacc_WuwWuhRuh(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdsaduh_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1227,7 +1226,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eq_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb) +#define Q6_Q_vcmp_eq_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1238,7 +1237,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and) +#define Q6_Q_vcmp_eqand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1249,7 +1248,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or) +#define Q6_Q_vcmp_eqor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1260,7 +1259,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor) +#define Q6_Q_vcmp_eqxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1271,7 +1270,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eq_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh) +#define Q6_Q_vcmp_eq_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1282,7 +1281,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and) +#define Q6_Q_vcmp_eqand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1293,7 +1292,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or) +#define Q6_Q_vcmp_eqor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1304,7 +1303,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor) +#define Q6_Q_vcmp_eqxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1315,7 +1314,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eq_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw) +#define Q6_Q_vcmp_eq_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1326,7 +1325,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and) +#define Q6_Q_vcmp_eqand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1337,7 +1336,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or) +#define Q6_Q_vcmp_eqor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1348,7 +1347,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_eqxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor) +#define Q6_Q_vcmp_eqxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_veqw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1359,7 +1358,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb) +#define Q6_Q_vcmp_gt_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1370,7 +1369,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and) +#define Q6_Q_vcmp_gtand_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1381,7 +1380,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or) +#define Q6_Q_vcmp_gtor_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1392,7 +1391,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor) +#define Q6_Q_vcmp_gtxacc_QVbVb(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtb_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1403,7 +1402,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth) +#define Q6_Q_vcmp_gt_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1414,7 +1413,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and) +#define Q6_Q_vcmp_gtand_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1425,7 +1424,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or) +#define Q6_Q_vcmp_gtor_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1436,7 +1435,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor) +#define Q6_Q_vcmp_gtxacc_QVhVh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgth_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1447,7 +1446,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub) +#define Q6_Q_vcmp_gt_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1458,7 +1457,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and) +#define Q6_Q_vcmp_gtand_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1469,7 +1468,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or) +#define Q6_Q_vcmp_gtor_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1480,7 +1479,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor) +#define Q6_Q_vcmp_gtxacc_QVubVub(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtub_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1491,7 +1490,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh) +#define Q6_Q_vcmp_gt_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1502,7 +1501,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and) +#define Q6_Q_vcmp_gtand_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1513,7 +1512,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or) +#define Q6_Q_vcmp_gtor_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1524,7 +1523,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor) +#define Q6_Q_vcmp_gtxacc_QVuhVuh(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuh_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1535,7 +1534,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw) +#define Q6_Q_vcmp_gt_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1546,7 +1545,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and) +#define Q6_Q_vcmp_gtand_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1557,7 +1556,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or) +#define Q6_Q_vcmp_gtor_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1568,7 +1567,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor) +#define Q6_Q_vcmp_gtxacc_QVuwVuw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtuw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1579,7 +1578,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gt_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw) +#define Q6_Q_vcmp_gt_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw)(Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1590,7 +1589,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtand_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and) +#define Q6_Q_vcmp_gtand_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1601,7 +1600,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtor_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or) +#define Q6_Q_vcmp_gtor_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1612,7 +1611,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vcmp_gtxacc_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor) +#define Q6_Q_vcmp_gtxacc_QVwVw(Qx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgtw_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qx),-1),Vu,Vv)),-1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1623,7 +1622,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vinsert_VwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr) +#define Q6_Vw_vinsert_VwR(Vx,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vinsertwr)(Vx,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1634,7 +1633,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vlalign_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb) +#define Q6_V_vlalign_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignb)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1645,7 +1644,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vlalign_VVI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi) +#define Q6_V_vlalign_VVI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlalignbi)(Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1656,7 +1655,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vlsr_VuhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh) +#define Q6_Vuh_vlsr_VuhR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1667,7 +1666,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vlsr_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv) +#define Q6_Vh_vlsr_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrhv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1678,7 +1677,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vlsr_VuwR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw) +#define Q6_Vuw_vlsr_VuwR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrw)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1689,7 +1688,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vlsr_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv) +#define Q6_Vw_vlsr_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrwv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1700,7 +1699,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vlut32_VbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb) +#define Q6_Vb_vlut32_VbVbR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1711,7 +1710,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vlut32or_VbVbVbR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc) +#define Q6_Vb_vlut32or_VbVbVbR(Vx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracc)(Vx,Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1722,7 +1721,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vlut16_VbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh) +#define Q6_Wh_vlut16_VbVhR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1733,7 +1732,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vlut16or_WhVbVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc) +#define Q6_Wh_vlut16or_WhVbVhR(Vxx,Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracc)(Vxx,Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1744,7 +1743,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vmax_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh) +#define Q6_Vh_vmax_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1755,7 +1754,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vmax_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub) +#define Q6_Vub_vmax_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1766,7 +1765,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vmax_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh) +#define Q6_Vuh_vmax_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1777,7 +1776,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vmax_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw) +#define Q6_Vw_vmax_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1788,7 +1787,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vmin_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh) +#define Q6_Vh_vmin_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1799,7 +1798,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vmin_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub) +#define Q6_Vub_vmin_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1810,7 +1809,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vmin_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh) +#define Q6_Vuh_vmin_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1821,7 +1820,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vmin_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw) +#define Q6_Vw_vmin_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1832,7 +1831,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpa_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus) +#define Q6_Wh_vmpa_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1843,7 +1842,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpaacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc) +#define Q6_Wh_vmpaacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabus_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1854,7 +1853,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpa_WubWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv) +#define Q6_Wh_vmpa_WubWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabusv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1865,7 +1864,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpa_WubWub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv) +#define Q6_Wh_vmpa_WubWub(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuuv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1876,7 +1875,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpa_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb) +#define Q6_Ww_vmpa_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1887,7 +1886,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpaacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc) +#define Q6_Ww_vmpaacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahb_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1898,7 +1897,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus) +#define Q6_Wh_vmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1909,7 +1908,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpyacc_WhVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc) +#define Q6_Wh_vmpyacc_WhVubRb(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybus_acc)(Vxx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1920,7 +1919,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv) +#define Q6_Wh_vmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1931,7 +1930,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpyacc_WhVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc) +#define Q6_Wh_vmpyacc_WhVubVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybusv_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1942,7 +1941,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv) +#define Q6_Wh_vmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1953,7 +1952,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpyacc_WhVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc) +#define Q6_Wh_vmpyacc_WhVbVb(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpybv_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1964,7 +1963,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh) +#define Q6_Vw_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1975,7 +1974,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpy_VhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh) +#define Q6_Ww_vmpy_VhRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1986,7 +1985,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpyacc_WwVhRh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc) +#define Q6_Ww_vmpyacc_WwVhRh_sat(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsat_acc)(Vxx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -1997,7 +1996,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpy_VhRh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs) +#define Q6_Vh_vmpy_VhRh_s1_rnd_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhsrs)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2008,7 +2007,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpy_VhRh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss) +#define Q6_Vh_vmpy_VhRh_s1_sat(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhss)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2019,7 +2018,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpy_VhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus) +#define Q6_Ww_vmpy_VhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2030,7 +2029,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpyacc_WwVhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc) +#define Q6_Ww_vmpyacc_WwVhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhus_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2041,7 +2040,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpy_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv) +#define Q6_Ww_vmpy_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2052,7 +2051,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpyacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc) +#define Q6_Ww_vmpyacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhv_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2063,7 +2062,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpy_VhVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs) +#define Q6_Vh_vmpy_VhVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyhvsrs)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2074,7 +2073,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyieo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh) +#define Q6_Vw_vmpyieo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyieoh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2085,7 +2084,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyieacc_VwVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc) +#define Q6_Vw_vmpyieacc_VwVwVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewh_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2096,7 +2095,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyie_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh) +#define Q6_Vw_vmpyie_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2107,7 +2106,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyieacc_VwVwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc) +#define Q6_Vw_vmpyieacc_VwVwVuh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiewuh_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2118,7 +2117,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpyi_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih) +#define Q6_Vh_vmpyi_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2129,7 +2128,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpyiacc_VhVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc) +#define Q6_Vh_vmpyiacc_VhVhVh(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyih_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2140,7 +2139,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpyi_VhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb) +#define Q6_Vh_vmpyi_VhRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2151,7 +2150,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vmpyiacc_VhVhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc) +#define Q6_Vh_vmpyiacc_VhVhRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyihb_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2162,7 +2161,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyio_VwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh) +#define Q6_Vw_vmpyio_VwVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiowh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2173,7 +2172,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyi_VwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb) +#define Q6_Vw_vmpyi_VwRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2184,7 +2183,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyiacc_VwVwRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc) +#define Q6_Vw_vmpyiacc_VwVwRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwb_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2195,7 +2194,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyi_VwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh) +#define Q6_Vw_vmpyi_VwRh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2206,7 +2205,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyiacc_VwVwRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc) +#define Q6_Vw_vmpyiacc_VwVwRh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwh_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2217,7 +2216,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyo_VwVh_s1_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh) +#define Q6_Vw_vmpyo_VwVh_s1_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2228,7 +2227,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd) +#define Q6_Vw_vmpyo_VwVh_s1_rnd_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2239,7 +2238,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc) +#define Q6_Vw_vmpyoacc_VwVwVh_s1_rnd_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_rnd_sacc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2250,7 +2249,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc) +#define Q6_Vw_vmpyoacc_VwVwVh_s1_sat_shift(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_sacc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2261,7 +2260,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuh_vmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub) +#define Q6_Wuh_vmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2272,7 +2271,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuh_vmpyacc_WuhVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc) +#define Q6_Wuh_vmpyacc_WuhVubRub(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyub_acc)(Vxx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2283,7 +2282,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuh_vmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv) +#define Q6_Wuh_vmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2294,7 +2293,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuh_vmpyacc_WuhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc) +#define Q6_Wuh_vmpyacc_WuhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyubv_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2305,7 +2304,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vmpy_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh) +#define Q6_Wuw_vmpy_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2316,7 +2315,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vmpyacc_WuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc) +#define Q6_Wuw_vmpyacc_WuwVuhRuh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuh_acc)(Vxx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2327,7 +2326,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vmpy_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv) +#define Q6_Wuw_vmpy_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2338,7 +2337,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vmpyacc_WuwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc) +#define Q6_Wuw_vmpyacc_WuwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhv_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2349,7 +2348,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vmux_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux) +#define Q6_V_vmux_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmux)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2360,7 +2359,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vnavg_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh) +#define Q6_Vh_vnavg_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2371,7 +2370,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vnavg_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub) +#define Q6_Vb_vnavg_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2382,7 +2381,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vnavg_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw) +#define Q6_Vw_vnavg_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2393,7 +2392,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vnormamt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth) +#define Q6_Vh_vnormamt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamth)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2404,7 +2403,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vnormamt_Vw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw) +#define Q6_Vw_vnormamt_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnormamtw)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2415,7 +2414,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vnot_V __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot) +#define Q6_V_vnot_V(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnot)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2426,7 +2425,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor) +#define Q6_V_vor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vor)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2437,7 +2436,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vpacke_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb) +#define Q6_Vb_vpacke_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2448,7 +2447,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vpacke_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh) +#define Q6_Vh_vpacke_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackeh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2459,7 +2458,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat) +#define Q6_Vb_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhb_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2470,7 +2469,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vpack_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat) +#define Q6_Vub_vpack_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackhub_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2481,7 +2480,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vpacko_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob) +#define Q6_Vb_vpacko_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackob)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2492,7 +2491,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vpacko_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh) +#define Q6_Vh_vpacko_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackoh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2503,7 +2502,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat) +#define Q6_Vh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwh_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2514,7 +2513,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vpack_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat) +#define Q6_Vuh_vpack_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpackwuh_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2525,7 +2524,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vpopcount_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth) +#define Q6_Vh_vpopcount_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vpopcounth)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2536,7 +2535,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vrdelta_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta) +#define Q6_V_vrdelta_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrdelta)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2547,7 +2546,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpy_VubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus) +#define Q6_Vw_vrmpy_VubRb(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2558,7 +2557,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpyacc_VwVubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc) +#define Q6_Vw_vrmpyacc_VwVubRb(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybus_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2569,7 +2568,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vrmpy_WubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi) +#define Q6_Ww_vrmpy_WubRbI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi)(Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2580,7 +2579,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vrmpyacc_WwWubRbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc) +#define Q6_Ww_vrmpyacc_WwWubRbI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusi_acc)(Vxx,Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2591,7 +2590,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpy_VubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv) +#define Q6_Vw_vrmpy_VubVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2602,7 +2601,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpyacc_VwVubVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc) +#define Q6_Vw_vrmpyacc_VwVubVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybusv_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2613,7 +2612,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpy_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv) +#define Q6_Vw_vrmpy_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2624,7 +2623,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vrmpyacc_VwVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc) +#define Q6_Vw_vrmpyacc_VwVbVb(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpybv_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2635,7 +2634,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vrmpy_VubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub) +#define Q6_Vuw_vrmpy_VubRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2646,7 +2645,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vrmpyacc_VuwVubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc) +#define Q6_Vuw_vrmpyacc_VuwVubRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyub_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2657,7 +2656,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vrmpy_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi) +#define Q6_Wuw_vrmpy_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi)(Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2668,7 +2667,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vrmpyacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc) +#define Q6_Wuw_vrmpyacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubi_acc)(Vxx,Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2679,7 +2678,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vrmpy_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv) +#define Q6_Vuw_vrmpy_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2690,7 +2689,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vrmpyacc_VuwVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc) +#define Q6_Vuw_vrmpyacc_VuwVubVub(Vx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrmpyubv_acc)(Vx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2701,7 +2700,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vror_VR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror) +#define Q6_V_vror_VR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vror)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2712,7 +2711,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb) +#define Q6_Vb_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2723,7 +2722,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vround_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub) +#define Q6_Vub_vround_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundhub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2734,7 +2733,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh) +#define Q6_Vh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2745,7 +2744,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vround_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh) +#define Q6_Vuh_vround_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vroundwuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2756,7 +2755,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vrsad_WubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi) +#define Q6_Wuw_vrsad_WubRubI(Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi)(Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2767,7 +2766,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wuw_vrsadacc_WuwWubRubI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc) +#define Q6_Wuw_vrsadacc_WuwWubRubI(Vxx,Vuu,Rt,Iu1) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrsadubi_acc)(Vxx,Vuu,Rt,Iu1) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2778,7 +2777,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vsat_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub) +#define Q6_Vub_vsat_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsathub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2789,7 +2788,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vsat_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh) +#define Q6_Vh_vsat_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatwh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2800,7 +2799,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vsxt_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb) +#define Q6_Wh_vsxt_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsb)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2811,7 +2810,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vsxt_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh) +#define Q6_Ww_vsxt_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2822,7 +2821,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vshuffe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh) +#define Q6_Vh_vshuffe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufeh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2833,7 +2832,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vshuff_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb) +#define Q6_Vb_vshuff_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffb)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2844,7 +2843,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vshuffe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb) +#define Q6_Vb_vshuffe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffeb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2855,7 +2854,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vshuff_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh) +#define Q6_Vh_vshuff_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2866,7 +2865,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vshuffo_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob) +#define Q6_Vb_vshuffo_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffob)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2877,7 +2876,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_vshuff_VVR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd) +#define Q6_W_vshuff_VVR(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshuffvdd)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2888,7 +2887,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wb_vshuffoe_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb) +#define Q6_Wb_vshuffoe_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2899,7 +2898,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vshuffoe_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh) +#define Q6_Wh_vshuffoe_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoeh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2910,7 +2909,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vshuffo_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh) +#define Q6_Vh_vshuffo_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vshufoh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2921,7 +2920,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vsub_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb) +#define Q6_Vb_vsub_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2932,7 +2931,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wb_vsub_WbWb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv) +#define Q6_Wb_vsub_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubb_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2943,7 +2942,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_condnac_QnVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq) +#define Q6_Vb_condnac_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2954,7 +2953,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_condnac_QVbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq) +#define Q6_Vb_condnac_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2965,7 +2964,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh) +#define Q6_Vh_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2976,7 +2975,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vsub_WhWh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv) +#define Q6_Wh_vsub_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubh_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2987,7 +2986,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_condnac_QnVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq) +#define Q6_Vh_condnac_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -2998,7 +2997,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_condnac_QVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq) +#define Q6_Vh_condnac_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3009,7 +3008,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vsub_VhVh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat) +#define Q6_Vh_vsub_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3020,7 +3019,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vsub_WhWh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv) +#define Q6_Wh_vsub_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3031,7 +3030,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vsub_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw) +#define Q6_Ww_vsub_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubhw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3042,7 +3041,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vsub_VubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh) +#define Q6_Wh_vsub_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3053,7 +3052,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vsub_VubVub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat) +#define Q6_Vub_vsub_VubVub_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3064,7 +3063,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wub_vsub_WubWub_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv) +#define Q6_Wub_vsub_WubWub_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsububsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3075,7 +3074,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vsub_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat) +#define Q6_Vuh_vsub_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3086,7 +3085,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuh_vsub_WuhWuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv) +#define Q6_Wuh_vsub_WuhWuh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3097,7 +3096,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vsub_VuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw) +#define Q6_Ww_vsub_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuhw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3108,7 +3107,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vsub_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw) +#define Q6_Vw_vsub_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3119,7 +3118,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vsub_WwWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv) +#define Q6_Ww_vsub_WwWw(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubw_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3130,7 +3129,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_condnac_QnVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq) +#define Q6_Vw_condnac_QnVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3141,7 +3140,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_condnac_QVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq) +#define Q6_Vw_condnac_QVwVw(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3152,7 +3151,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vsub_VwVw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat) +#define Q6_Vw_vsub_VwVw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3163,7 +3162,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vsub_WwWw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv) +#define Q6_Ww_vsub_WwWw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubwsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3174,7 +3173,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_vswap_QVV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap) +#define Q6_W_vswap_QVV(Qt,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vswap)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1),Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3185,7 +3184,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vtmpy_WbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb) +#define Q6_Wh_vtmpy_WbRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3196,7 +3195,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vtmpyacc_WhWbRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc) +#define Q6_Wh_vtmpyacc_WhWbRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyb_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3207,7 +3206,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vtmpy_WubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus) +#define Q6_Wh_vtmpy_WubRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3218,7 +3217,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vtmpyacc_WhWubRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc) +#define Q6_Wh_vtmpyacc_WhWubRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpybus_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3229,7 +3228,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vtmpy_WhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb) +#define Q6_Ww_vtmpy_WhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3240,7 +3239,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vtmpyacc_WwWhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc) +#define Q6_Ww_vtmpyacc_WwWhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vtmpyhb_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3251,7 +3250,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vunpack_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb) +#define Q6_Wh_vunpack_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackb)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3262,7 +3261,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vunpack_Vh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh) +#define Q6_Ww_vunpack_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3273,7 +3272,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vunpackoor_WhVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob) +#define Q6_Wh_vunpackoor_WhVb(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackob)(Vxx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3284,7 +3283,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vunpackoor_WwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh) +#define Q6_Ww_vunpackoor_WwVh(Vxx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackoh)(Vxx,Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3295,7 +3294,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuh_vunpack_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub) +#define Q6_Wuh_vunpack_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackub)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3306,7 +3305,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuw_vunpack_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh) +#define Q6_Wuw_vunpack_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vunpackuh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3317,7 +3316,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vxor_VV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor) +#define Q6_V_vxor_VV(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vxor)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3328,7 +3327,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuh_vzxt_Vub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb) +#define Q6_Wuh_vzxt_Vub(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzb)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 60 @@ -3339,7 +3338,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuw_vzxt_Vuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh) +#define Q6_Wuw_vzxt_Vuh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vzh)(Vu) #endif /* __HEXAGON_ARCH___ >= 60 */ #if __HVX_ARCH__ >= 62 @@ -3350,7 +3349,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vb_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb) +#define Q6_Vb_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatb)(Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3361,7 +3360,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vh_vsplat_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath) +#define Q6_Vh_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplath)(Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3372,7 +3371,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Q_vsetq2_R __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2) +#define Q6_Q_vsetq2_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2v2)(Rt)),-1) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3383,7 +3382,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Qb_vshuffe_QhQh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh) +#define Q6_Qb_vshuffe_QhQh(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3394,7 +3393,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Qh_vshuffe_QwQw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw) +#define Q6_Qh_vshuffe_QwQw(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_shuffeqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3405,7 +3404,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vadd_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat) +#define Q6_Vb_vadd_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3416,7 +3415,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wb_vadd_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv) +#define Q6_Wb_vadd_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3427,7 +3426,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vadd_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry) +#define Q6_Vw_vadd_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarry)(Vu,Vv,Qx) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3438,7 +3437,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vadd_vclb_VhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh) +#define Q6_Vh_vadd_vclb_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3449,7 +3448,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vadd_vclb_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw) +#define Q6_Vw_vadd_vclb_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddclbw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3460,7 +3459,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vaddacc_WwVhVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc) +#define Q6_Ww_vaddacc_WwVhVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3471,7 +3470,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vaddacc_WhVubVub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc) +#define Q6_Wh_vaddacc_WhVubVub(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3482,7 +3481,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vadd_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat) +#define Q6_Vub_vadd_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddububb_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3493,7 +3492,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vaddacc_WwVuhVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc) +#define Q6_Ww_vaddacc_WwVuhVuh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduhw_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3504,7 +3503,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vadd_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat) +#define Q6_Vuw_vadd_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3515,7 +3514,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuw_vadd_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv) +#define Q6_Wuw_vadd_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vadduwsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3526,7 +3525,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_V_vand_QnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt) +#define Q6_V_vand_QnR(Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3537,7 +3536,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_V_vandor_VQnR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc) +#define Q6_V_vandor_VQnR(Vx,Qu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandnqrt_acc)(Vx,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qu),-1),Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3548,7 +3547,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vand_QnV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv) +#define Q6_V_vand_QnV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvnqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3559,7 +3558,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_V_vand_QV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv) +#define Q6_V_vand_QV(Qv,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvqv)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vu) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3570,7 +3569,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vasr_VhVhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat) +#define Q6_Vb_vasr_VhVhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrhbsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3581,7 +3580,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vasr_VuwVuwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat) +#define Q6_Vuh_vasr_VuwVuwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3592,7 +3591,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vasr_VwVwR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat) +#define Q6_Vuh_vasr_VwVwR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrwuhrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3603,7 +3602,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vlsr_VubR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb) +#define Q6_Vub_vlsr_VubR(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlsrb)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3614,7 +3613,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vlut32_VbVbR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm) +#define Q6_Vb_vlut32_VbVbR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_nm)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3625,7 +3624,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vlut32or_VbVbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci) +#define Q6_Vb_vlut32or_VbVbVbI(Vx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvb_oracci)(Vx,Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3636,7 +3635,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vlut32_VbVbI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi) +#define Q6_Vb_vlut32_VbVbI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvvbi)(Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3647,7 +3646,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vlut16_VbVhR_nomatch __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm) +#define Q6_Wh_vlut16_VbVhR_nomatch(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_nm)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3658,7 +3657,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vlut16or_WhVbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci) +#define Q6_Wh_vlut16or_WhVbVhI(Vxx,Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwh_oracci)(Vxx,Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3669,7 +3668,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wh_vlut16_VbVhI __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi) +#define Q6_Wh_vlut16_VbVhI(Vu,Vv,Iu3) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlutvwhi)(Vu,Vv,Iu3) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3680,7 +3679,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vmax_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb) +#define Q6_Vb_vmax_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmaxb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3691,7 +3690,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vmin_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb) +#define Q6_Vb_vmin_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vminb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3702,7 +3701,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpa_WuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb) +#define Q6_Ww_vmpa_WuhRb(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3713,7 +3712,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpaacc_WwWuhRb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc) +#define Q6_Ww_vmpaacc_WwWuhRb(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhb_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3724,7 +3723,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_W_vmpye_VwVuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64) +#define Q6_W_vmpye_VwVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyewuh_64)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3735,7 +3734,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyi_VwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub) +#define Q6_Vw_vmpyi_VwRub(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3746,7 +3745,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vw_vmpyiacc_VwVwRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc) +#define Q6_Vw_vmpyiacc_VwVwRub(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyiwub_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3757,7 +3756,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_W_vmpyoacc_WVwVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc) +#define Q6_W_vmpyoacc_WVwVh(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyowh_64_acc)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3768,7 +3767,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vround_VuhVuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub) +#define Q6_Vub_vround_VuhVuh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduhub)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3779,7 +3778,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vround_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh) +#define Q6_Vuh_vround_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrounduwuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3790,7 +3789,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vsat_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh) +#define Q6_Vuh_vsat_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatuwuh)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3801,7 +3800,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vsub_VbVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat) +#define Q6_Vb_vsub_VbVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3812,7 +3811,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wb_vsub_WbWb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv) +#define Q6_Wb_vsub_WbWb_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubbsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3823,7 +3822,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vsub_VwVwQ_carry __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry) +#define Q6_Vw_vsub_VwVwQ_carry(Vu,Vv,Qx) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubcarry)(Vu,Vv,Qx) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3834,7 +3833,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vsub_VubVb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat) +#define Q6_Vub_vsub_VubVb_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubububb_sat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3845,7 +3844,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vsub_VuwVuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat) +#define Q6_Vuw_vsub_VuwVuw_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 62 @@ -3856,7 +3855,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Wuw_vsub_WuwWuw_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv) +#define Q6_Wuw_vsub_WuwWuw_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsubuwsat_dv)(Vuu,Vvv) #endif /* __HEXAGON_ARCH___ >= 62 */ #if __HVX_ARCH__ >= 65 @@ -3867,7 +3866,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vabs_Vb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb) +#define Q6_Vb_vabs_Vb(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb)(Vu) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3878,7 +3877,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vabs_Vb_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat) +#define Q6_Vb_vabs_Vb_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsb_sat)(Vu) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3889,7 +3888,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vaslacc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc) +#define Q6_Vh_vaslacc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaslh_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3900,7 +3899,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_vasracc_VhVhR __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc) +#define Q6_Vh_vasracc_VhVhR(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasrh_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3911,7 +3910,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vasr_VuhVuhR_rnd_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat) +#define Q6_Vub_vasr_VuhVuhR_rnd_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubrndsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3922,7 +3921,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vub_vasr_VuhVuhR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat) +#define Q6_Vub_vasr_VuhVuhR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruhubsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3933,7 +3932,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuh_vasr_VuwVuwR_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat) +#define Q6_Vuh_vasr_VuwVuwR_sat(Vu,Vv,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasruwuhsat)(Vu,Vv,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3944,7 +3943,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb) +#define Q6_Vb_vavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3955,7 +3954,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vavg_VbVb_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd) +#define Q6_Vb_vavg_VbVb_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavgbrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3966,7 +3965,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vavg_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw) +#define Q6_Vuw_vavg_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3977,7 +3976,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vavg_VuwVuw_rnd __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd) +#define Q6_Vuw_vavg_VuwVuw_rnd(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vavguwrnd)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3988,7 +3987,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_W_vzero __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0) +#define Q6_W_vzero() __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vdd0)() #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -3999,7 +3998,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_ARMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh) +#define Q6_vgather_ARMVh(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermh)(Rs,Rt,Mu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4010,7 +4009,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_AQRMVh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq) +#define Q6_vgather_AQRMVh(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4021,7 +4020,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_ARMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw) +#define Q6_vgather_ARMWw(Rs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhw)(Rs,Rt,Mu,Vvv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4032,7 +4031,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_AQRMWw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq) +#define Q6_vgather_AQRMWw(Rs,Qs,Rt,Mu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermhwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4043,7 +4042,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_ARMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw) +#define Q6_vgather_ARMVw(Rs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermw)(Rs,Rt,Mu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4054,7 +4053,7 @@ Execution Slots: SLOT01 ========================================================================== */ -#define Q6_vgather_AQRMVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq) +#define Q6_vgather_AQRMVw(Rs,Qs,Rt,Mu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vgathermwq)(Rs,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4065,7 +4064,7 @@ Execution Slots: SLOT2 ========================================================================== */ -#define Q6_Vh_vlut4_VuhPh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4) +#define Q6_Vh_vlut4_VuhPh(Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vlut4)(Vu,Rtt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4076,7 +4075,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpa_WubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu) +#define Q6_Wh_vmpa_WubRub(Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu)(Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4087,7 +4086,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Wh_vmpaacc_WhWubRub __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc) +#define Q6_Wh_vmpaacc_WhWubRub(Vxx,Vuu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpabuu_acc)(Vxx,Vuu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4098,7 +4097,7 @@ Execution Slots: SLOT2 ========================================================================== */ -#define Q6_Vh_vmpa_VhVhVhPh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat) +#define Q6_Vh_vmpa_VhVhVhPh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpahhsat)(Vx,Vu,Rtt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4109,7 +4108,7 @@ Execution Slots: SLOT2 ========================================================================== */ -#define Q6_Vh_vmpa_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat) +#define Q6_Vh_vmpa_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpauhuhsat)(Vx,Vu,Rtt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4120,7 +4119,7 @@ Execution Slots: SLOT2 ========================================================================== */ -#define Q6_Vh_vmps_VhVhVuhPuh_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat) +#define Q6_Vh_vmps_VhVhVuhPuh_sat(Vx,Vu,Rtt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpsuhuhsat)(Vx,Vu,Rtt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4131,7 +4130,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_vmpyacc_WwVhRh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc) +#define Q6_Ww_vmpyacc_WwVhRh(Vxx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyh_acc)(Vxx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4142,7 +4141,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vmpye_VuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe) +#define Q6_Vuw_vmpye_VuhRuh(Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe)(Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4153,7 +4152,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Vuw_vmpyeacc_VuwVuhRuh __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc) +#define Q6_Vuw_vmpyeacc_VuwVuhRuh(Vx,Vu,Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vmpyuhe_acc)(Vx,Vu,Rt) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4164,7 +4163,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_vnavg_VbVb __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb) +#define Q6_Vb_vnavg_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vnavgb)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4175,7 +4174,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vb_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb) +#define Q6_Vb_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqb)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4186,7 +4185,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vh_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh) +#define Q6_Vh_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqh)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4197,7 +4196,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_prefixsum_Q __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw) +#define Q6_Vw_prefixsum_Q(Qv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vprefixqw)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1)) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4208,7 +4207,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh) +#define Q6_vscatter_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh)(Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4219,7 +4218,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatteracc_RMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add) +#define Q6_vscatteracc_RMVhV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermh_add)(Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4230,7 +4229,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_QRMVhV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq) +#define Q6_vscatter_QRMVhV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4241,7 +4240,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw) +#define Q6_vscatter_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw)(Rt,Mu,Vvv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4252,7 +4251,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatteracc_RMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add) +#define Q6_vscatteracc_RMWwV(Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhw_add)(Rt,Mu,Vvv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4263,7 +4262,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_QRMWwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq) +#define Q6_vscatter_QRMWwV(Qs,Rt,Mu,Vvv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermhwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vvv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4274,7 +4273,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw) +#define Q6_vscatter_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw)(Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4285,7 +4284,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatteracc_RMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add) +#define Q6_vscatteracc_RMVwV(Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermw_add)(Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 65 @@ -4296,7 +4295,7 @@ Execution Slots: SLOT0 ========================================================================== */ -#define Q6_vscatter_QRMVwV __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq) +#define Q6_vscatter_QRMVwV(Qs,Rt,Mu,Vv,Vw) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vscattermwq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),Rt,Mu,Vv,Vw) #endif /* __HEXAGON_ARCH___ >= 65 */ #if __HVX_ARCH__ >= 66 @@ -4307,7 +4306,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vadd_VwVwQ_carry_sat __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat) +#define Q6_Vw_vadd_VwVwQ_carry_sat(Vu,Vv,Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddcarrysat)(Vu,Vv,__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1)) #endif /* __HEXAGON_ARCH___ >= 66 */ #if __HVX_ARCH__ >= 66 @@ -4318,7 +4317,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Ww_vasrinto_WwVwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into) +#define Q6_Ww_vasrinto_WwVwVw(Vxx,Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vasr_into)(Vxx,Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 66 */ #if __HVX_ARCH__ >= 66 @@ -4329,7 +4328,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vuw_vrotr_VuwVuw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr) +#define Q6_Vuw_vrotr_VuwVuw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vrotr)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 66 */ #if __HVX_ARCH__ >= 66 @@ -4340,7 +4339,7 @@ Execution Slots: SLOT0123 ========================================================================== */ -#define Q6_Vw_vsatdw_VwVw __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw) +#define Q6_Vw_vsatdw_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vsatdw)(Vu,Vv) #endif /* __HEXAGON_ARCH___ >= 66 */ #if __HVX_ARCH__ >= 68 @@ -4351,7 +4350,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_v6mpy_WubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10) +#define Q6_Ww_v6mpy_WubWbI_h(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10)(Vuu,Vvv,Iu2) #endif /* __HEXAGON_ARCH___ >= 68 */ #if __HVX_ARCH__ >= 68 @@ -4362,7 +4361,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_v6mpyacc_WwWubWbI_h __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx) +#define Q6_Ww_v6mpyacc_WwWubWbI_h(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyhubs10_vxx)(Vxx,Vuu,Vvv,Iu2) #endif /* __HEXAGON_ARCH___ >= 68 */ #if __HVX_ARCH__ >= 68 @@ -4373,7 +4372,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_v6mpy_WubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10) +#define Q6_Ww_v6mpy_WubWbI_v(Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10)(Vuu,Vvv,Iu2) #endif /* __HEXAGON_ARCH___ >= 68 */ #if __HVX_ARCH__ >= 68 @@ -4384,7 +4383,7 @@ Execution Slots: SLOT23 ========================================================================== */ -#define Q6_Ww_v6mpyacc_WwWubWbI_v __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx) +#define Q6_Ww_v6mpyacc_WwWubWbI_v(Vxx,Vuu,Vvv,Iu2) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_v6mpyvubs10_vxx)(Vxx,Vuu,Vvv,Iu2) #endif /* __HEXAGON_ARCH___ >= 68 */ #endif /* __HVX__ */ diff --git a/clang/test/CodeGen/builtins-hexagon-v66-128B.c b/clang/test/CodeGen/builtins-hexagon-v66-128B.c index 074728ec07ec..5839d3ae975e 100644 --- a/clang/test/CodeGen/builtins-hexagon-v66-128B.c +++ b/clang/test/CodeGen/builtins-hexagon-v66-128B.c @@ -20,7 +20,7 @@ HEXAGON_Vect1024 test1(void *in, void *out) { v2 = *p++; q1 = *p++; - return __builtin_HEXAGON_V6_vaddcarrysat_128B(v1, v2, q1); + return __builtin_HEXAGON_V6_vaddcarrysat_128B(v1, v2, __builtin_HEXAGON_V6_vandvrt_128B(q1, -1)); } // CHECK-LABEL: @test26 diff --git a/clang/test/CodeGen/builtins-hexagon-v66.c b/clang/test/CodeGen/builtins-hexagon-v66.c index 767f9faf7702..a222228dd683 100644 --- a/clang/test/CodeGen/builtins-hexagon-v66.c +++ b/clang/test/CodeGen/builtins-hexagon-v66.c @@ -44,7 +44,7 @@ HEXAGON_Vect512 test5(void *in, void *out) { v2 = *p++; q1 = *p++; - return __builtin_HEXAGON_V6_vaddcarrysat(v1, v2, q1); + return __builtin_HEXAGON_V6_vaddcarrysat(v1, v2, __builtin_HEXAGON_V6_vandvrt(q1, -1)); } // CHECK-LABEL: @test6 diff --git a/clang/test/CodeGen/builtins-hvx128.c b/clang/test/CodeGen/builtins-hvx128.c index d61afdefc2ae..226f6c0792a7 100644 --- a/clang/test/CodeGen/builtins-hvx128.c +++ b/clang/test/CodeGen/builtins-hvx128.c @@ -6,6 +6,17 @@ void test() { int v128 __attribute__((__vector_size__(128))); int v256 __attribute__((__vector_size__(256))); + // These are special and ugly: they take an HVX vector in place of + // the HVX vector predicate. + // CHECK: @llvm.hexagon.V6.vmaskedstorenq.128B + __builtin_HEXAGON_V6_vmaskedstorenq_128B(q128, 0, v128); + // CHECK: @llvm.hexagon.V6.vmaskedstorentnq.128B + __builtin_HEXAGON_V6_vmaskedstorentnq_128B(q128, 0, v128); + // CHECK: @llvm.hexagon.V6.vmaskedstorentq.128B + __builtin_HEXAGON_V6_vmaskedstorentq_128B(q128, 0, v128); + // CHECK: @llvm.hexagon.V6.vmaskedstoreq.128B + __builtin_HEXAGON_V6_vmaskedstoreq_128B(q128, 0, v128); + // CHECK: @llvm.hexagon.V6.extractw.128B __builtin_HEXAGON_V6_extractw_128B(v128, 0); // CHECK: @llvm.hexagon.V6.hi.128B @@ -19,33 +30,33 @@ void test() { // CHECK: @llvm.hexagon.V6.lvsplatw.128B __builtin_HEXAGON_V6_lvsplatw_128B(0); // CHECK: @llvm.hexagon.V6.pred.and.128B - __builtin_HEXAGON_V6_pred_and_128B(q128, q128); + __builtin_HEXAGON_V6_pred_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.pred.and.n.128B - __builtin_HEXAGON_V6_pred_and_n_128B(q128, q128); + __builtin_HEXAGON_V6_pred_and_n_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.pred.not.128B - __builtin_HEXAGON_V6_pred_not_128B(q128); + __builtin_HEXAGON_V6_pred_not_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.pred.or.128B - __builtin_HEXAGON_V6_pred_or_128B(q128, q128); + __builtin_HEXAGON_V6_pred_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.pred.or.n.128B - __builtin_HEXAGON_V6_pred_or_n_128B(q128, q128); + __builtin_HEXAGON_V6_pred_or_n_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.pred.scalar2.128B __builtin_HEXAGON_V6_pred_scalar2_128B(0); // CHECK: @llvm.hexagon.V6.pred.scalar2v2.128B __builtin_HEXAGON_V6_pred_scalar2v2_128B(0); // CHECK: @llvm.hexagon.V6.pred.xor.128B - __builtin_HEXAGON_V6_pred_xor_128B(q128, q128); + __builtin_HEXAGON_V6_pred_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.shuffeqh.128B - __builtin_HEXAGON_V6_shuffeqh_128B(q128, q128); + __builtin_HEXAGON_V6_shuffeqh_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.shuffeqw.128B - __builtin_HEXAGON_V6_shuffeqw_128B(q128, q128); + __builtin_HEXAGON_V6_shuffeqw_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), __builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.vS32b.nqpred.ai.128B - __builtin_HEXAGON_V6_vS32b_nqpred_ai_128B(q128, 0, v128); + __builtin_HEXAGON_V6_vS32b_nqpred_ai_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, v128); // CHECK: @llvm.hexagon.V6.vS32b.nt.nqpred.ai.128B - __builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B(q128, 0, v128); + __builtin_HEXAGON_V6_vS32b_nt_nqpred_ai_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, v128); // CHECK: @llvm.hexagon.V6.vS32b.nt.qpred.ai.128B - __builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B(q128, 0, v128); + __builtin_HEXAGON_V6_vS32b_nt_qpred_ai_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, v128); // CHECK: @llvm.hexagon.V6.vS32b.qpred.ai.128B - __builtin_HEXAGON_V6_vS32b_qpred_ai_128B(q128, 0, v128); + __builtin_HEXAGON_V6_vS32b_qpred_ai_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, v128); // CHECK: @llvm.hexagon.V6.vabsb.128B __builtin_HEXAGON_V6_vabsb_128B(v128); // CHECK: @llvm.hexagon.V6.vabsb.sat.128B @@ -71,9 +82,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddb.dv.128B __builtin_HEXAGON_V6_vaddb_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vaddbnq.128B - __builtin_HEXAGON_V6_vaddbnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddbnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddbq.128B - __builtin_HEXAGON_V6_vaddbq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddbq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddbsat.128B __builtin_HEXAGON_V6_vaddbsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vaddbsat.dv.128B @@ -89,9 +100,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddh.dv.128B __builtin_HEXAGON_V6_vaddh_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vaddhnq.128B - __builtin_HEXAGON_V6_vaddhnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddhnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddhq.128B - __builtin_HEXAGON_V6_vaddhq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddhq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddhsat.128B __builtin_HEXAGON_V6_vaddhsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vaddhsat.dv.128B @@ -127,9 +138,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddw.dv.128B __builtin_HEXAGON_V6_vaddw_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vaddwnq.128B - __builtin_HEXAGON_V6_vaddwnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddwnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddwq.128B - __builtin_HEXAGON_V6_vaddwq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vaddwq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vaddwsat.128B __builtin_HEXAGON_V6_vaddwsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vaddwsat.dv.128B @@ -141,21 +152,21 @@ void test() { // CHECK: @llvm.hexagon.V6.vand.128B __builtin_HEXAGON_V6_vand_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vandnqrt.128B - __builtin_HEXAGON_V6_vandnqrt_128B(q128, 0); + __builtin_HEXAGON_V6_vandnqrt_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0); // CHECK: @llvm.hexagon.V6.vandnqrt.acc.128B - __builtin_HEXAGON_V6_vandnqrt_acc_128B(v128, q128, 0); + __builtin_HEXAGON_V6_vandnqrt_acc_128B(v128, __builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0); // CHECK: @llvm.hexagon.V6.vandqrt.128B - __builtin_HEXAGON_V6_vandqrt_128B(q128, 0); + __builtin_HEXAGON_V6_vandqrt_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0); // CHECK: @llvm.hexagon.V6.vandqrt.acc.128B - __builtin_HEXAGON_V6_vandqrt_acc_128B(v128, q128, 0); + __builtin_HEXAGON_V6_vandqrt_acc_128B(v128, __builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0); // CHECK: @llvm.hexagon.V6.vandvnqv.128B - __builtin_HEXAGON_V6_vandvnqv_128B(q128, v128); + __builtin_HEXAGON_V6_vandvnqv_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128); // CHECK: @llvm.hexagon.V6.vandvqv.128B - __builtin_HEXAGON_V6_vandvqv_128B(q128, v128); + __builtin_HEXAGON_V6_vandvqv_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128); // CHECK: @llvm.hexagon.V6.vandvrt.128B __builtin_HEXAGON_V6_vandvrt_128B(v128, 0); // CHECK: @llvm.hexagon.V6.vandvrt.acc.128B - __builtin_HEXAGON_V6_vandvrt_acc_128B(q128, v128, 0); + __builtin_HEXAGON_V6_vandvrt_acc_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, 0); // CHECK: @llvm.hexagon.V6.vaslh.128B __builtin_HEXAGON_V6_vaslh_128B(v128, 0); // CHECK: @llvm.hexagon.V6.vaslh.acc.128B @@ -297,87 +308,87 @@ void test() { // CHECK: @llvm.hexagon.V6.veqb.128B __builtin_HEXAGON_V6_veqb_128B(v128, v128); // CHECK: @llvm.hexagon.V6.veqb.and.128B - __builtin_HEXAGON_V6_veqb_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqb_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqb.or.128B - __builtin_HEXAGON_V6_veqb_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqb_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqb.xor.128B - __builtin_HEXAGON_V6_veqb_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqb_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqh.128B __builtin_HEXAGON_V6_veqh_128B(v128, v128); // CHECK: @llvm.hexagon.V6.veqh.and.128B - __builtin_HEXAGON_V6_veqh_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqh_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqh.or.128B - __builtin_HEXAGON_V6_veqh_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqh_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqh.xor.128B - __builtin_HEXAGON_V6_veqh_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqh_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqw.128B __builtin_HEXAGON_V6_veqw_128B(v128, v128); // CHECK: @llvm.hexagon.V6.veqw.and.128B - __builtin_HEXAGON_V6_veqw_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqw_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqw.or.128B - __builtin_HEXAGON_V6_veqw_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqw_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.veqw.xor.128B - __builtin_HEXAGON_V6_veqw_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_veqw_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgathermh.128B __builtin_HEXAGON_V6_vgathermh_128B(0, 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgathermhq.128B - __builtin_HEXAGON_V6_vgathermhq_128B(0, q128, 0, 0, v128); + __builtin_HEXAGON_V6_vgathermhq_128B(0, __builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgathermhw.128B __builtin_HEXAGON_V6_vgathermhw_128B(0, 0, 0, v256); // CHECK: @llvm.hexagon.V6.vgathermhwq.128B - __builtin_HEXAGON_V6_vgathermhwq_128B(0, q128, 0, 0, v256); + __builtin_HEXAGON_V6_vgathermhwq_128B(0, __builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v256); // CHECK: @llvm.hexagon.V6.vgathermw.128B __builtin_HEXAGON_V6_vgathermw_128B(0, 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgathermwq.128B - __builtin_HEXAGON_V6_vgathermwq_128B(0, q128, 0, 0, v128); + __builtin_HEXAGON_V6_vgathermwq_128B(0, __builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgtb.128B __builtin_HEXAGON_V6_vgtb_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgtb.and.128B - __builtin_HEXAGON_V6_vgtb_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtb_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtb.or.128B - __builtin_HEXAGON_V6_vgtb_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtb_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtb.xor.128B - __builtin_HEXAGON_V6_vgtb_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtb_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgth.128B __builtin_HEXAGON_V6_vgth_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgth.and.128B - __builtin_HEXAGON_V6_vgth_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgth_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgth.or.128B - __builtin_HEXAGON_V6_vgth_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgth_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgth.xor.128B - __builtin_HEXAGON_V6_vgth_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgth_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtub.128B __builtin_HEXAGON_V6_vgtub_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgtub.and.128B - __builtin_HEXAGON_V6_vgtub_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtub_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtub.or.128B - __builtin_HEXAGON_V6_vgtub_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtub_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtub.xor.128B - __builtin_HEXAGON_V6_vgtub_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtub_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuh.128B __builtin_HEXAGON_V6_vgtuh_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgtuh.and.128B - __builtin_HEXAGON_V6_vgtuh_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuh_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuh.or.128B - __builtin_HEXAGON_V6_vgtuh_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuh_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuh.xor.128B - __builtin_HEXAGON_V6_vgtuh_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuh_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuw.128B __builtin_HEXAGON_V6_vgtuw_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgtuw.and.128B - __builtin_HEXAGON_V6_vgtuw_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuw_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuw.or.128B - __builtin_HEXAGON_V6_vgtuw_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuw_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtuw.xor.128B - __builtin_HEXAGON_V6_vgtuw_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtuw_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtw.128B __builtin_HEXAGON_V6_vgtw_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vgtw.and.128B - __builtin_HEXAGON_V6_vgtw_and_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtw_and_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtw.or.128B - __builtin_HEXAGON_V6_vgtw_or_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtw_or_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vgtw.xor.128B - __builtin_HEXAGON_V6_vgtw_xor_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vgtw_xor_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vinsertwr.128B __builtin_HEXAGON_V6_vinsertwr_128B(v128, 0); // CHECK: @llvm.hexagon.V6.vlalignb.128B @@ -416,14 +427,6 @@ void test() { __builtin_HEXAGON_V6_vlutvwh_oracci_128B(v256, v128, v128, 0); // CHECK: @llvm.hexagon.V6.vlutvwhi.128B __builtin_HEXAGON_V6_vlutvwhi_128B(v128, v128, 0); - // CHECK: @llvm.hexagon.V6.vmaskedstorenq.128B - __builtin_HEXAGON_V6_vmaskedstorenq_128B(q128, 0, v128); - // CHECK: @llvm.hexagon.V6.vmaskedstorentnq.128B - __builtin_HEXAGON_V6_vmaskedstorentnq_128B(q128, 0, v128); - // CHECK: @llvm.hexagon.V6.vmaskedstorentq.128B - __builtin_HEXAGON_V6_vmaskedstorentq_128B(q128, 0, v128); - // CHECK: @llvm.hexagon.V6.vmaskedstoreq.128B - __builtin_HEXAGON_V6_vmaskedstoreq_128B(q128, 0, v128); // CHECK: @llvm.hexagon.V6.vmaxb.128B __builtin_HEXAGON_V6_vmaxb_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vmaxh.128B @@ -567,7 +570,7 @@ void test() { // CHECK: @llvm.hexagon.V6.vmpyuhv.acc.128B __builtin_HEXAGON_V6_vmpyuhv_acc_128B(v256, v128, v128); // CHECK: @llvm.hexagon.V6.vmux.128B - __builtin_HEXAGON_V6_vmux_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vmux_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vnavgb.128B __builtin_HEXAGON_V6_vnavgb_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vnavgh.128B @@ -603,11 +606,11 @@ void test() { // CHECK: @llvm.hexagon.V6.vpopcounth.128B __builtin_HEXAGON_V6_vpopcounth_128B(v128); // CHECK: @llvm.hexagon.V6.vprefixqb.128B - __builtin_HEXAGON_V6_vprefixqb_128B(q128); + __builtin_HEXAGON_V6_vprefixqb_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.vprefixqh.128B - __builtin_HEXAGON_V6_vprefixqh_128B(q128); + __builtin_HEXAGON_V6_vprefixqh_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.vprefixqw.128B - __builtin_HEXAGON_V6_vprefixqw_128B(q128); + __builtin_HEXAGON_V6_vprefixqw_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1)); // CHECK: @llvm.hexagon.V6.vrdelta.128B __builtin_HEXAGON_V6_vrdelta_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vrmpybub.rtt.128B @@ -677,19 +680,19 @@ void test() { // CHECK: @llvm.hexagon.V6.vscattermh.add.128B __builtin_HEXAGON_V6_vscattermh_add_128B(0, 0, v128, v128); // CHECK: @llvm.hexagon.V6.vscattermhq.128B - __builtin_HEXAGON_V6_vscattermhq_128B(q128, 0, 0, v128, v128); + __builtin_HEXAGON_V6_vscattermhq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v128, v128); // CHECK: @llvm.hexagon.V6.vscattermhw.128B __builtin_HEXAGON_V6_vscattermhw_128B(0, 0, v256, v128); // CHECK: @llvm.hexagon.V6.vscattermhw.add.128B __builtin_HEXAGON_V6_vscattermhw_add_128B(0, 0, v256, v128); // CHECK: @llvm.hexagon.V6.vscattermhwq.128B - __builtin_HEXAGON_V6_vscattermhwq_128B(q128, 0, 0, v256, v128); + __builtin_HEXAGON_V6_vscattermhwq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v256, v128); // CHECK: @llvm.hexagon.V6.vscattermw.128B __builtin_HEXAGON_V6_vscattermw_128B(0, 0, v128, v128); // CHECK: @llvm.hexagon.V6.vscattermw.add.128B __builtin_HEXAGON_V6_vscattermw_add_128B(0, 0, v128, v128); // CHECK: @llvm.hexagon.V6.vscattermwq.128B - __builtin_HEXAGON_V6_vscattermwq_128B(q128, 0, 0, v128, v128); + __builtin_HEXAGON_V6_vscattermwq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), 0, 0, v128, v128); // CHECK: @llvm.hexagon.V6.vsh.128B __builtin_HEXAGON_V6_vsh_128B(v128); // CHECK: @llvm.hexagon.V6.vshufeh.128B @@ -715,9 +718,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubb.dv.128B __builtin_HEXAGON_V6_vsubb_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vsubbnq.128B - __builtin_HEXAGON_V6_vsubbnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubbnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubbq.128B - __builtin_HEXAGON_V6_vsubbq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubbq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubbsat.128B __builtin_HEXAGON_V6_vsubbsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vsubbsat.dv.128B @@ -729,9 +732,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubh.dv.128B __builtin_HEXAGON_V6_vsubh_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vsubhnq.128B - __builtin_HEXAGON_V6_vsubhnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubhnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubhq.128B - __builtin_HEXAGON_V6_vsubhq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubhq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubhsat.128B __builtin_HEXAGON_V6_vsubhsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vsubhsat.dv.128B @@ -761,15 +764,15 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubw.dv.128B __builtin_HEXAGON_V6_vsubw_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vsubwnq.128B - __builtin_HEXAGON_V6_vsubwnq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubwnq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubwq.128B - __builtin_HEXAGON_V6_vsubwq_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vsubwq_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vsubwsat.128B __builtin_HEXAGON_V6_vsubwsat_128B(v128, v128); // CHECK: @llvm.hexagon.V6.vsubwsat.dv.128B __builtin_HEXAGON_V6_vsubwsat_dv_128B(v256, v256); // CHECK: @llvm.hexagon.V6.vswap.128B - __builtin_HEXAGON_V6_vswap_128B(q128, v128, v128); + __builtin_HEXAGON_V6_vswap_128B(__builtin_HEXAGON_V6_vandvrt_128B(q128, -1), v128, v128); // CHECK: @llvm.hexagon.V6.vtmpyb.128B __builtin_HEXAGON_V6_vtmpyb_128B(v256, 0); // CHECK: @llvm.hexagon.V6.vtmpyb.acc.128B diff --git a/clang/test/CodeGen/builtins-hvx64.c b/clang/test/CodeGen/builtins-hvx64.c index 27d39990adb5..7321460c489e 100644 --- a/clang/test/CodeGen/builtins-hvx64.c +++ b/clang/test/CodeGen/builtins-hvx64.c @@ -6,6 +6,17 @@ void test() { int v64 __attribute__((__vector_size__(64))); int v128 __attribute__((__vector_size__(128))); + // These are special and ugly: they take an HVX vector in place of + // the HVX vector predicate. + // CHECK: @llvm.hexagon.V6.vmaskedstorenq + __builtin_HEXAGON_V6_vmaskedstorenq(q64, 0, v64); + // CHECK: @llvm.hexagon.V6.vmaskedstorentnq + __builtin_HEXAGON_V6_vmaskedstorentnq(q64, 0, v64); + // CHECK: @llvm.hexagon.V6.vmaskedstorentq + __builtin_HEXAGON_V6_vmaskedstorentq(q64, 0, v64); + // CHECK: @llvm.hexagon.V6.vmaskedstoreq + __builtin_HEXAGON_V6_vmaskedstoreq(q64, 0, v64); + // CHECK: @llvm.hexagon.V6.extractw __builtin_HEXAGON_V6_extractw(v64, 0); // CHECK: @llvm.hexagon.V6.hi @@ -19,33 +30,33 @@ void test() { // CHECK: @llvm.hexagon.V6.lvsplatw __builtin_HEXAGON_V6_lvsplatw(0); // CHECK: @llvm.hexagon.V6.pred.and - __builtin_HEXAGON_V6_pred_and(q64, q64); + __builtin_HEXAGON_V6_pred_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.pred.and.n - __builtin_HEXAGON_V6_pred_and_n(q64, q64); + __builtin_HEXAGON_V6_pred_and_n(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.pred.not - __builtin_HEXAGON_V6_pred_not(q64); + __builtin_HEXAGON_V6_pred_not(__builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.pred.or - __builtin_HEXAGON_V6_pred_or(q64, q64); + __builtin_HEXAGON_V6_pred_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.pred.or.n - __builtin_HEXAGON_V6_pred_or_n(q64, q64); + __builtin_HEXAGON_V6_pred_or_n(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.pred.scalar2 __builtin_HEXAGON_V6_pred_scalar2(0); // CHECK: @llvm.hexagon.V6.pred.scalar2v2 __builtin_HEXAGON_V6_pred_scalar2v2(0); // CHECK: @llvm.hexagon.V6.pred.xor - __builtin_HEXAGON_V6_pred_xor(q64, q64); + __builtin_HEXAGON_V6_pred_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.shuffeqh - __builtin_HEXAGON_V6_shuffeqh(q64, q64); + __builtin_HEXAGON_V6_shuffeqh(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.shuffeqw - __builtin_HEXAGON_V6_shuffeqw(q64, q64); + __builtin_HEXAGON_V6_shuffeqw(__builtin_HEXAGON_V6_vandvrt(q64, -1), __builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.vS32b.nqpred.ai - __builtin_HEXAGON_V6_vS32b_nqpred_ai(q64, 0, v64); + __builtin_HEXAGON_V6_vS32b_nqpred_ai(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, v64); // CHECK: @llvm.hexagon.V6.vS32b.nt.nqpred.ai - __builtin_HEXAGON_V6_vS32b_nt_nqpred_ai(q64, 0, v64); + __builtin_HEXAGON_V6_vS32b_nt_nqpred_ai(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, v64); // CHECK: @llvm.hexagon.V6.vS32b.nt.qpred.ai - __builtin_HEXAGON_V6_vS32b_nt_qpred_ai(q64, 0, v64); + __builtin_HEXAGON_V6_vS32b_nt_qpred_ai(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, v64); // CHECK: @llvm.hexagon.V6.vS32b.qpred.ai - __builtin_HEXAGON_V6_vS32b_qpred_ai(q64, 0, v64); + __builtin_HEXAGON_V6_vS32b_qpred_ai(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, v64); // CHECK: @llvm.hexagon.V6.vabsb __builtin_HEXAGON_V6_vabsb(v64); // CHECK: @llvm.hexagon.V6.vabsb.sat @@ -71,9 +82,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddb.dv __builtin_HEXAGON_V6_vaddb_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vaddbnq - __builtin_HEXAGON_V6_vaddbnq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddbnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddbq - __builtin_HEXAGON_V6_vaddbq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddbq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddbsat __builtin_HEXAGON_V6_vaddbsat(v64, v64); // CHECK: @llvm.hexagon.V6.vaddbsat.dv @@ -89,9 +100,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddh.dv __builtin_HEXAGON_V6_vaddh_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vaddhnq - __builtin_HEXAGON_V6_vaddhnq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddhnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddhq - __builtin_HEXAGON_V6_vaddhq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddhq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddhsat __builtin_HEXAGON_V6_vaddhsat(v64, v64); // CHECK: @llvm.hexagon.V6.vaddhsat.dv @@ -127,9 +138,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vaddw.dv __builtin_HEXAGON_V6_vaddw_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vaddwnq - __builtin_HEXAGON_V6_vaddwnq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddwnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddwq - __builtin_HEXAGON_V6_vaddwq(q64, v64, v64); + __builtin_HEXAGON_V6_vaddwq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vaddwsat __builtin_HEXAGON_V6_vaddwsat(v64, v64); // CHECK: @llvm.hexagon.V6.vaddwsat.dv @@ -141,21 +152,21 @@ void test() { // CHECK: @llvm.hexagon.V6.vand __builtin_HEXAGON_V6_vand(v64, v64); // CHECK: @llvm.hexagon.V6.vandnqrt - __builtin_HEXAGON_V6_vandnqrt(q64, 0); + __builtin_HEXAGON_V6_vandnqrt(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0); // CHECK: @llvm.hexagon.V6.vandnqrt.acc - __builtin_HEXAGON_V6_vandnqrt_acc(v64, q64, 0); + __builtin_HEXAGON_V6_vandnqrt_acc(v64, __builtin_HEXAGON_V6_vandvrt(q64, -1), 0); // CHECK: @llvm.hexagon.V6.vandqrt - __builtin_HEXAGON_V6_vandqrt(q64, 0); + __builtin_HEXAGON_V6_vandqrt(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0); // CHECK: @llvm.hexagon.V6.vandqrt.acc - __builtin_HEXAGON_V6_vandqrt_acc(v64, q64, 0); + __builtin_HEXAGON_V6_vandqrt_acc(v64, __builtin_HEXAGON_V6_vandvrt(q64, -1), 0); // CHECK: @llvm.hexagon.V6.vandvnqv - __builtin_HEXAGON_V6_vandvnqv(q64, v64); + __builtin_HEXAGON_V6_vandvnqv(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64); // CHECK: @llvm.hexagon.V6.vandvqv - __builtin_HEXAGON_V6_vandvqv(q64, v64); + __builtin_HEXAGON_V6_vandvqv(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64); // CHECK: @llvm.hexagon.V6.vandvrt __builtin_HEXAGON_V6_vandvrt(v64, 0); // CHECK: @llvm.hexagon.V6.vandvrt.acc - __builtin_HEXAGON_V6_vandvrt_acc(q64, v64, 0); + __builtin_HEXAGON_V6_vandvrt_acc(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, 0); // CHECK: @llvm.hexagon.V6.vaslh __builtin_HEXAGON_V6_vaslh(v64, 0); // CHECK: @llvm.hexagon.V6.vaslh.acc @@ -297,87 +308,87 @@ void test() { // CHECK: @llvm.hexagon.V6.veqb __builtin_HEXAGON_V6_veqb(v64, v64); // CHECK: @llvm.hexagon.V6.veqb.and - __builtin_HEXAGON_V6_veqb_and(q64, v64, v64); + __builtin_HEXAGON_V6_veqb_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqb.or - __builtin_HEXAGON_V6_veqb_or(q64, v64, v64); + __builtin_HEXAGON_V6_veqb_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqb.xor - __builtin_HEXAGON_V6_veqb_xor(q64, v64, v64); + __builtin_HEXAGON_V6_veqb_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqh __builtin_HEXAGON_V6_veqh(v64, v64); // CHECK: @llvm.hexagon.V6.veqh.and - __builtin_HEXAGON_V6_veqh_and(q64, v64, v64); + __builtin_HEXAGON_V6_veqh_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqh.or - __builtin_HEXAGON_V6_veqh_or(q64, v64, v64); + __builtin_HEXAGON_V6_veqh_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqh.xor - __builtin_HEXAGON_V6_veqh_xor(q64, v64, v64); + __builtin_HEXAGON_V6_veqh_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqw __builtin_HEXAGON_V6_veqw(v64, v64); // CHECK: @llvm.hexagon.V6.veqw.and - __builtin_HEXAGON_V6_veqw_and(q64, v64, v64); + __builtin_HEXAGON_V6_veqw_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqw.or - __builtin_HEXAGON_V6_veqw_or(q64, v64, v64); + __builtin_HEXAGON_V6_veqw_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.veqw.xor - __builtin_HEXAGON_V6_veqw_xor(q64, v64, v64); + __builtin_HEXAGON_V6_veqw_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgathermh __builtin_HEXAGON_V6_vgathermh(0, 0, 0, v64); // CHECK: @llvm.hexagon.V6.vgathermhq - __builtin_HEXAGON_V6_vgathermhq(0, q64, 0, 0, v64); + __builtin_HEXAGON_V6_vgathermhq(0, __builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v64); // CHECK: @llvm.hexagon.V6.vgathermhw __builtin_HEXAGON_V6_vgathermhw(0, 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgathermhwq - __builtin_HEXAGON_V6_vgathermhwq(0, q64, 0, 0, v128); + __builtin_HEXAGON_V6_vgathermhwq(0, __builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v128); // CHECK: @llvm.hexagon.V6.vgathermw __builtin_HEXAGON_V6_vgathermw(0, 0, 0, v64); // CHECK: @llvm.hexagon.V6.vgathermwq - __builtin_HEXAGON_V6_vgathermwq(0, q64, 0, 0, v64); + __builtin_HEXAGON_V6_vgathermwq(0, __builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v64); // CHECK: @llvm.hexagon.V6.vgtb __builtin_HEXAGON_V6_vgtb(v64, v64); // CHECK: @llvm.hexagon.V6.vgtb.and - __builtin_HEXAGON_V6_vgtb_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgtb_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtb.or - __builtin_HEXAGON_V6_vgtb_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgtb_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtb.xor - __builtin_HEXAGON_V6_vgtb_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgtb_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgth __builtin_HEXAGON_V6_vgth(v64, v64); // CHECK: @llvm.hexagon.V6.vgth.and - __builtin_HEXAGON_V6_vgth_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgth_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgth.or - __builtin_HEXAGON_V6_vgth_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgth_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgth.xor - __builtin_HEXAGON_V6_vgth_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgth_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtub __builtin_HEXAGON_V6_vgtub(v64, v64); // CHECK: @llvm.hexagon.V6.vgtub.and - __builtin_HEXAGON_V6_vgtub_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgtub_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtub.or - __builtin_HEXAGON_V6_vgtub_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgtub_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtub.xor - __builtin_HEXAGON_V6_vgtub_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgtub_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuh __builtin_HEXAGON_V6_vgtuh(v64, v64); // CHECK: @llvm.hexagon.V6.vgtuh.and - __builtin_HEXAGON_V6_vgtuh_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuh_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuh.or - __builtin_HEXAGON_V6_vgtuh_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuh_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuh.xor - __builtin_HEXAGON_V6_vgtuh_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuh_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuw __builtin_HEXAGON_V6_vgtuw(v64, v64); // CHECK: @llvm.hexagon.V6.vgtuw.and - __builtin_HEXAGON_V6_vgtuw_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuw_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuw.or - __builtin_HEXAGON_V6_vgtuw_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuw_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtuw.xor - __builtin_HEXAGON_V6_vgtuw_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgtuw_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtw __builtin_HEXAGON_V6_vgtw(v64, v64); // CHECK: @llvm.hexagon.V6.vgtw.and - __builtin_HEXAGON_V6_vgtw_and(q64, v64, v64); + __builtin_HEXAGON_V6_vgtw_and(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtw.or - __builtin_HEXAGON_V6_vgtw_or(q64, v64, v64); + __builtin_HEXAGON_V6_vgtw_or(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vgtw.xor - __builtin_HEXAGON_V6_vgtw_xor(q64, v64, v64); + __builtin_HEXAGON_V6_vgtw_xor(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vinsertwr __builtin_HEXAGON_V6_vinsertwr(v64, 0); // CHECK: @llvm.hexagon.V6.vlalignb @@ -416,14 +427,6 @@ void test() { __builtin_HEXAGON_V6_vlutvwh_oracci(v128, v64, v64, 0); // CHECK: @llvm.hexagon.V6.vlutvwhi __builtin_HEXAGON_V6_vlutvwhi(v64, v64, 0); - // CHECK: @llvm.hexagon.V6.vmaskedstorenq - __builtin_HEXAGON_V6_vmaskedstorenq(q64, 0, v64); - // CHECK: @llvm.hexagon.V6.vmaskedstorentnq - __builtin_HEXAGON_V6_vmaskedstorentnq(q64, 0, v64); - // CHECK: @llvm.hexagon.V6.vmaskedstorentq - __builtin_HEXAGON_V6_vmaskedstorentq(q64, 0, v64); - // CHECK: @llvm.hexagon.V6.vmaskedstoreq - __builtin_HEXAGON_V6_vmaskedstoreq(q64, 0, v64); // CHECK: @llvm.hexagon.V6.vmaxb __builtin_HEXAGON_V6_vmaxb(v64, v64); // CHECK: @llvm.hexagon.V6.vmaxh @@ -567,7 +570,7 @@ void test() { // CHECK: @llvm.hexagon.V6.vmpyuhv.acc __builtin_HEXAGON_V6_vmpyuhv_acc(v128, v64, v64); // CHECK: @llvm.hexagon.V6.vmux - __builtin_HEXAGON_V6_vmux(q64, v64, v64); + __builtin_HEXAGON_V6_vmux(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vnavgb __builtin_HEXAGON_V6_vnavgb(v64, v64); // CHECK: @llvm.hexagon.V6.vnavgh @@ -603,11 +606,11 @@ void test() { // CHECK: @llvm.hexagon.V6.vpopcounth __builtin_HEXAGON_V6_vpopcounth(v64); // CHECK: @llvm.hexagon.V6.vprefixqb - __builtin_HEXAGON_V6_vprefixqb(q64); + __builtin_HEXAGON_V6_vprefixqb(__builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.vprefixqh - __builtin_HEXAGON_V6_vprefixqh(q64); + __builtin_HEXAGON_V6_vprefixqh(__builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.vprefixqw - __builtin_HEXAGON_V6_vprefixqw(q64); + __builtin_HEXAGON_V6_vprefixqw(__builtin_HEXAGON_V6_vandvrt(q64, -1)); // CHECK: @llvm.hexagon.V6.vrdelta __builtin_HEXAGON_V6_vrdelta(v64, v64); // CHECK: @llvm.hexagon.V6.vrmpybub.rtt @@ -677,19 +680,19 @@ void test() { // CHECK: @llvm.hexagon.V6.vscattermh.add __builtin_HEXAGON_V6_vscattermh_add(0, 0, v64, v64); // CHECK: @llvm.hexagon.V6.vscattermhq - __builtin_HEXAGON_V6_vscattermhq(q64, 0, 0, v64, v64); + __builtin_HEXAGON_V6_vscattermhq(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v64, v64); // CHECK: @llvm.hexagon.V6.vscattermhw __builtin_HEXAGON_V6_vscattermhw(0, 0, v128, v64); // CHECK: @llvm.hexagon.V6.vscattermhw.add __builtin_HEXAGON_V6_vscattermhw_add(0, 0, v128, v64); // CHECK: @llvm.hexagon.V6.vscattermhwq - __builtin_HEXAGON_V6_vscattermhwq(q64, 0, 0, v128, v64); + __builtin_HEXAGON_V6_vscattermhwq(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v128, v64); // CHECK: @llvm.hexagon.V6.vscattermw __builtin_HEXAGON_V6_vscattermw(0, 0, v64, v64); // CHECK: @llvm.hexagon.V6.vscattermw.add __builtin_HEXAGON_V6_vscattermw_add(0, 0, v64, v64); // CHECK: @llvm.hexagon.V6.vscattermwq - __builtin_HEXAGON_V6_vscattermwq(q64, 0, 0, v64, v64); + __builtin_HEXAGON_V6_vscattermwq(__builtin_HEXAGON_V6_vandvrt(q64, -1), 0, 0, v64, v64); // CHECK: @llvm.hexagon.V6.vsh __builtin_HEXAGON_V6_vsh(v64); // CHECK: @llvm.hexagon.V6.vshufeh @@ -715,9 +718,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubb.dv __builtin_HEXAGON_V6_vsubb_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vsubbnq - __builtin_HEXAGON_V6_vsubbnq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubbnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubbq - __builtin_HEXAGON_V6_vsubbq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubbq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubbsat __builtin_HEXAGON_V6_vsubbsat(v64, v64); // CHECK: @llvm.hexagon.V6.vsubbsat.dv @@ -729,9 +732,9 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubh.dv __builtin_HEXAGON_V6_vsubh_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vsubhnq - __builtin_HEXAGON_V6_vsubhnq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubhnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubhq - __builtin_HEXAGON_V6_vsubhq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubhq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubhsat __builtin_HEXAGON_V6_vsubhsat(v64, v64); // CHECK: @llvm.hexagon.V6.vsubhsat.dv @@ -761,15 +764,15 @@ void test() { // CHECK: @llvm.hexagon.V6.vsubw.dv __builtin_HEXAGON_V6_vsubw_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vsubwnq - __builtin_HEXAGON_V6_vsubwnq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubwnq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubwq - __builtin_HEXAGON_V6_vsubwq(q64, v64, v64); + __builtin_HEXAGON_V6_vsubwq(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vsubwsat __builtin_HEXAGON_V6_vsubwsat(v64, v64); // CHECK: @llvm.hexagon.V6.vsubwsat.dv __builtin_HEXAGON_V6_vsubwsat_dv(v128, v128); // CHECK: @llvm.hexagon.V6.vswap - __builtin_HEXAGON_V6_vswap(q64, v64, v64); + __builtin_HEXAGON_V6_vswap(__builtin_HEXAGON_V6_vandvrt(q64, -1), v64, v64); // CHECK: @llvm.hexagon.V6.vtmpyb __builtin_HEXAGON_V6_vtmpyb(v128, 0); // CHECK: @llvm.hexagon.V6.vtmpyb.acc diff --git a/llvm/include/llvm/IR/IntrinsicsHexagonDep.td b/llvm/include/llvm/IR/IntrinsicsHexagonDep.td index 6799273bf805..8f0f743d1dec 100644 --- a/llvm/include/llvm/IR/IntrinsicsHexagonDep.td +++ b/llvm/include/llvm/IR/IntrinsicsHexagonDep.td @@ -23,13 +23,6 @@ class Hexagon_i64_i64_Intrinsic; // tag : A2_add -class Hexagon_custom_i32_i32i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty], - intr_properties>; - -// tag : A2_addh_h16_hh class Hexagon_i32_i32i32_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; // tag : A2_addp -class Hexagon_custom_i64_i64i64_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_i64_ty], [llvm_i64_ty,llvm_i64_ty], - intr_properties>; - -// tag : A2_addpsat class Hexagon_i64_i64i64_Intrinsic intr_properties = [IntrNoMem]> : Hexagon_Intrinsic; -// tag : A2_neg -class Hexagon_custom_i32_i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_i32_ty], [llvm_i32_ty], - intr_properties>; - // tag : A2_roundsat class Hexagon_i32_i64_Intrinsic intr_properties = [IntrNoMem]> @@ -288,20 +267,6 @@ class Hexagon_i64_i64i32i32_Intrinsic; -// tag : M2_dpmpyss_s0 -class Hexagon_custom_i64_i32i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_i64_ty], [llvm_i32_ty,llvm_i32_ty], - intr_properties>; - -// tag : S2_asl_i_p -class Hexagon_custom_i64_i64i32_Intrinsic< - list intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< - [llvm_i64_ty], [llvm_i64_ty,llvm_i32_ty], - intr_properties>; - // tag : S2_insert class Hexagon_i32_i32i32i32i32_Intrinsic intr_properties = [IntrNoMem]> @@ -366,44 +331,44 @@ class Hexagon_v32i32_i32_Intrinsic; // tag : V6_pred_and -class Hexagon_custom_v64i1_v64i1v64i1_Intrinsic< +class Hexagon_v64i1_v64i1v64i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_pred_and -class Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B< +class Hexagon_v128i1_v128i1v128i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_pred_not -class Hexagon_custom_v64i1_v64i1_Intrinsic< +class Hexagon_v64i1_v64i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_pred_not -class Hexagon_custom_v128i1_v128i1_Intrinsic_128B< +class Hexagon_v128i1_v128i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_pred_scalar2 -class Hexagon_custom_v64i1_i32_Intrinsic< +class Hexagon_v64i1_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_pred_scalar2 -class Hexagon_custom_v128i1_i32_Intrinsic_128B< +class Hexagon_v128i1_i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -436,16 +401,16 @@ class Hexagon_v64i32_v64i32v64i32v64i32i32_Intrinsic; // tag : V6_vS32b_nqpred_ai -class Hexagon_custom__v64i1ptrv16i32_Intrinsic< +class Hexagon__v64i1ptrv16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vS32b_nqpred_ai -class Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B< +class Hexagon__v128i1ptrv32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -485,16 +450,16 @@ class Hexagon_v64i32_v64i32v64i32_Intrinsic; // tag : V6_vaddbnq -class Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic< +class Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vaddbnq -class Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B< +class Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -513,16 +478,16 @@ class Hexagon_custom_v32i32v128i1_v32i32v32i32v128i1_Intrinsic_128B< intr_properties>; // tag : V6_vaddcarrysat -class Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic< +class Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vaddcarrysat -class Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B< +class Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -562,72 +527,72 @@ class Hexagon_v16i32_v16i32v16i32i32_Intrinsic; // tag : V6_vandnqrt -class Hexagon_custom_v16i32_v64i1i32_Intrinsic< +class Hexagon_v16i32_v64i1i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandnqrt -class Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B< +class Hexagon_v32i32_v128i1i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandnqrt_acc -class Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic< +class Hexagon_v16i32_v16i32v64i1i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandnqrt_acc -class Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B< +class Hexagon_v32i32_v32i32v128i1i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvnqv -class Hexagon_custom_v16i32_v64i1v16i32_Intrinsic< +class Hexagon_v16i32_v64i1v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvnqv -class Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B< +class Hexagon_v32i32_v128i1v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvrt -class Hexagon_custom_v64i1_v16i32i32_Intrinsic< +class Hexagon_v64i1_v16i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvrt -class Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B< +class Hexagon_v128i1_v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvrt_acc -class Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic< +class Hexagon_v64i1_v64i1v16i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vandvrt_acc -class Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B< +class Hexagon_v128i1_v128i1v32i32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -737,30 +702,30 @@ class Hexagon_v32i32_v32i32v32i32v32i32_Intrinsic; // tag : V6_veqb -class Hexagon_custom_v64i1_v16i32v16i32_Intrinsic< +class Hexagon_v64i1_v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_veqb -class Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B< +class Hexagon_v128i1_v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_veqb_and -class Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic< +class Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_veqb_and -class Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B< +class Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -779,16 +744,16 @@ class Hexagon__ptri32i32v32i32_Intrinsic; // tag : V6_vgathermhq -class Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic< +class Hexagon__ptrv64i1i32i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vgathermhq -class Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B< +class Hexagon__ptrv128i1i32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -800,16 +765,16 @@ class Hexagon__ptri32i32v64i32_Intrinsic; // tag : V6_vgathermhwq -class Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic< +class Hexagon__ptrv64i1i32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vgathermhwq -class Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B< +class Hexagon__ptrv128i1i32i32v64i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -891,16 +856,16 @@ class Hexagon_v64i32_v64i32v32i32i32_Intrinsic; // tag : V6_vprefixqb -class Hexagon_custom_v16i32_v64i1_Intrinsic< +class Hexagon_v16i32_v64i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vprefixqb -class Hexagon_custom_v32i32_v128i1_Intrinsic_128B< +class Hexagon_v32i32_v128i1_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -961,16 +926,16 @@ class Hexagon__i32i32v32i32v32i32_Intrinsic; // tag : V6_vscattermhq -class Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic< +class Hexagon__v64i1i32i32v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vscattermhq -class Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B< +class Hexagon__v128i1i32i32v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -989,30 +954,30 @@ class Hexagon__i32i32v64i32v32i32_Intrinsic; // tag : V6_vscattermhwq -class Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic< +class Hexagon__v64i1i32i32v32i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vscattermhwq -class Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B< +class Hexagon__v128i1i32i32v64i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vswap -class Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic< +class Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; // tag : V6_vswap -class Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B< +class Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic intr_properties = [IntrNoMem]> - : Hexagon_NonGCC_Intrinsic< + : Hexagon_Intrinsic; @@ -1077,7 +1042,7 @@ def int_hexagon_A2_abssat : Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_abssat">; def int_hexagon_A2_add : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_add">; def int_hexagon_A2_addh_h16_hh : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_h16_hh">; @@ -1116,10 +1081,10 @@ def int_hexagon_A2_addh_l16_sat_ll : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addh_l16_sat_ll">; def int_hexagon_A2_addi : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_addi", [IntrNoMem, ImmArg>]>; def int_hexagon_A2_addp : -Hexagon_custom_i64_i64i64_Intrinsic; +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addp">; def int_hexagon_A2_addpsat : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_addpsat">; @@ -1131,10 +1096,10 @@ def int_hexagon_A2_addsp : Hexagon_i64_i32i64_Intrinsic<"HEXAGON_A2_addsp">; def int_hexagon_A2_and : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_and">; def int_hexagon_A2_andir : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_andir", [IntrNoMem, ImmArg>]>; def int_hexagon_A2_andp : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_andp">; @@ -1188,7 +1153,7 @@ def int_hexagon_A2_minup : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_minup">; def int_hexagon_A2_neg : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_neg">; def int_hexagon_A2_negp : Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_negp">; @@ -1197,16 +1162,16 @@ def int_hexagon_A2_negsat : Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_negsat">; def int_hexagon_A2_not : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_not">; def int_hexagon_A2_notp : Hexagon_i64_i64_Intrinsic<"HEXAGON_A2_notp">; def int_hexagon_A2_or : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_or">; def int_hexagon_A2_orir : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_orir", [IntrNoMem, ImmArg>]>; def int_hexagon_A2_orp : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_orp">; @@ -1230,7 +1195,7 @@ def int_hexagon_A2_satuh : Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_satuh">; def int_hexagon_A2_sub : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_sub">; def int_hexagon_A2_subh_h16_hh : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_h16_hh">; @@ -1269,10 +1234,10 @@ def int_hexagon_A2_subh_l16_sat_ll : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subh_l16_sat_ll">; def int_hexagon_A2_subp : -Hexagon_custom_i64_i64i64_Intrinsic; +Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_subp">; def int_hexagon_A2_subri : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subri", [IntrNoMem, ImmArg>]>; def int_hexagon_A2_subsat : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_subsat">; @@ -1308,10 +1273,10 @@ def int_hexagon_A2_swiz : Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_swiz">; def int_hexagon_A2_sxtb : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxtb">; def int_hexagon_A2_sxth : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_sxth">; def int_hexagon_A2_sxtw : Hexagon_i64_i32_Intrinsic<"HEXAGON_A2_sxtw">; @@ -1524,16 +1489,16 @@ def int_hexagon_A2_vsubws : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_vsubws">; def int_hexagon_A2_xor : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A2_xor">; def int_hexagon_A2_xorp : Hexagon_i64_i64i64_Intrinsic<"HEXAGON_A2_xorp">; def int_hexagon_A2_zxtb : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxtb">; def int_hexagon_A2_zxth : -Hexagon_custom_i32_i32_Intrinsic; +Hexagon_i32_i32_Intrinsic<"HEXAGON_A2_zxth">; def int_hexagon_A4_andn : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_A4_andn">; @@ -2088,7 +2053,7 @@ def int_hexagon_M2_dpmpyss_rnd_s0 : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_rnd_s0">; def int_hexagon_M2_dpmpyss_s0 : -Hexagon_custom_i64_i32i32_Intrinsic; +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyss_s0">; def int_hexagon_M2_dpmpyuu_acc_s0 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_acc_s0">; @@ -2097,7 +2062,7 @@ def int_hexagon_M2_dpmpyuu_nac_s0 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_nac_s0">; def int_hexagon_M2_dpmpyuu_s0 : -Hexagon_custom_i64_i32i32_Intrinsic; +Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_dpmpyuu_s0">; def int_hexagon_M2_hmmpyh_rs1 : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_hmmpyh_rs1">; @@ -2514,10 +2479,10 @@ def int_hexagon_M2_mpyd_rnd_ll_s1 : Hexagon_i64_i32i32_Intrinsic<"HEXAGON_M2_mpyd_rnd_ll_s1">; def int_hexagon_M2_mpyi : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyi">; def int_hexagon_M2_mpysmi : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysmi", [IntrNoMem, ImmArg>]>; def int_hexagon_M2_mpysu_up : Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpysu_up">; @@ -2670,7 +2635,7 @@ def int_hexagon_M2_mpyud_nac_ll_s1 : Hexagon_i64_i64i32i32_Intrinsic<"HEXAGON_M2_mpyud_nac_ll_s1">; def int_hexagon_M2_mpyui : -Hexagon_custom_i32_i32i32_Intrinsic; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_M2_mpyui">; def int_hexagon_M2_nacci : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_M2_nacci">; @@ -2958,7 +2923,7 @@ def int_hexagon_S2_addasl_rrri : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_addasl_rrri", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p : -Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_i_p", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_p_acc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_acc", [IntrNoMem, ImmArg>]>; @@ -2976,7 +2941,7 @@ def int_hexagon_S2_asl_i_p_xacc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asl_i_p_xacc", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_r : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asl_i_r", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asl_i_r_acc : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asl_i_r_acc", [IntrNoMem, ImmArg>]>; @@ -3045,7 +3010,7 @@ def int_hexagon_S2_asl_r_vw : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asl_r_vw">; def int_hexagon_S2_asr_i_p : -Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asr_i_p_acc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_acc", [IntrNoMem, ImmArg>]>; @@ -3066,7 +3031,7 @@ def int_hexagon_S2_asr_i_p_rnd_goodsyntax : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_asr_i_p_rnd_goodsyntax", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asr_i_r : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_asr_i_r", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_asr_i_r_acc : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_asr_i_r_acc", [IntrNoMem, ImmArg>]>; @@ -3258,7 +3223,7 @@ def int_hexagon_S2_lsl_r_vw : Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsl_r_vw">; def int_hexagon_S2_lsr_i_p : -Hexagon_custom_i64_i64i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i64_i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_lsr_i_p_acc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_acc", [IntrNoMem, ImmArg>]>; @@ -3276,7 +3241,7 @@ def int_hexagon_S2_lsr_i_p_xacc : Hexagon_i64_i64i64i32_Intrinsic<"HEXAGON_S2_lsr_i_p_xacc", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_lsr_i_r : -Hexagon_custom_i32_i32i32_Intrinsic<[IntrNoMem, ImmArg>]>; +Hexagon_i32_i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r", [IntrNoMem, ImmArg>]>; def int_hexagon_S2_lsr_i_r_acc : Hexagon_i32_i32i32i32_Intrinsic<"HEXAGON_S2_lsr_i_r_acc", [IntrNoMem, ImmArg>]>; @@ -3809,70 +3774,70 @@ def int_hexagon_V6_lvsplatw_128B : Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplatw_128B">; def int_hexagon_V6_pred_and : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and">; def int_hexagon_V6_pred_and_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_128B">; def int_hexagon_V6_pred_and_n : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_and_n">; def int_hexagon_V6_pred_and_n_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_and_n_128B">; def int_hexagon_V6_pred_not : -Hexagon_custom_v64i1_v64i1_Intrinsic; +Hexagon_v64i1_v64i1_Intrinsic<"HEXAGON_V6_pred_not">; def int_hexagon_V6_pred_not_128B : -Hexagon_custom_v128i1_v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1_Intrinsic<"HEXAGON_V6_pred_not_128B">; def int_hexagon_V6_pred_or : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or">; def int_hexagon_V6_pred_or_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_128B">; def int_hexagon_V6_pred_or_n : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_or_n">; def int_hexagon_V6_pred_or_n_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_or_n_128B">; def int_hexagon_V6_pred_scalar2 : -Hexagon_custom_v64i1_i32_Intrinsic; +Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2">; def int_hexagon_V6_pred_scalar2_128B : -Hexagon_custom_v128i1_i32_Intrinsic_128B; +Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2_128B">; def int_hexagon_V6_pred_xor : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_pred_xor">; def int_hexagon_V6_pred_xor_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_pred_xor_128B">; def int_hexagon_V6_vS32b_nqpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai", [IntrWriteMem]>; def int_hexagon_V6_vS32b_nqpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nqpred_ai_128B", [IntrWriteMem]>; def int_hexagon_V6_vS32b_nt_nqpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai", [IntrWriteMem]>; def int_hexagon_V6_vS32b_nt_nqpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_nqpred_ai_128B", [IntrWriteMem]>; def int_hexagon_V6_vS32b_nt_qpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai", [IntrWriteMem]>; def int_hexagon_V6_vS32b_nt_qpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_nt_qpred_ai_128B", [IntrWriteMem]>; def int_hexagon_V6_vS32b_qpred_ai : -Hexagon_custom__v64i1ptrv16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1ptrv16i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai", [IntrWriteMem]>; def int_hexagon_V6_vS32b_qpred_ai_128B : -Hexagon_custom__v128i1ptrv32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1ptrv32i32_Intrinsic<"HEXAGON_V6_vS32b_qpred_ai_128B", [IntrWriteMem]>; def int_hexagon_V6_vabsdiffh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vabsdiffh">; @@ -3935,16 +3900,16 @@ def int_hexagon_V6_vaddb_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddb_dv_128B">; def int_hexagon_V6_vaddbnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbnq">; def int_hexagon_V6_vaddbnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbnq_128B">; def int_hexagon_V6_vaddbq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbq">; def int_hexagon_V6_vaddbq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddbq_128B">; def int_hexagon_V6_vaddh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddh">; @@ -3959,16 +3924,16 @@ def int_hexagon_V6_vaddh_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddh_dv_128B">; def int_hexagon_V6_vaddhnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhnq">; def int_hexagon_V6_vaddhnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhnq_128B">; def int_hexagon_V6_vaddhq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhq">; def int_hexagon_V6_vaddhq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddhq_128B">; def int_hexagon_V6_vaddhsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddhsat">; @@ -4037,16 +4002,16 @@ def int_hexagon_V6_vaddw_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vaddw_dv_128B">; def int_hexagon_V6_vaddwnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwnq">; def int_hexagon_V6_vaddwnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwnq_128B">; def int_hexagon_V6_vaddwq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwq">; def int_hexagon_V6_vaddwq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vaddwq_128B">; def int_hexagon_V6_vaddwsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddwsat">; @@ -4079,28 +4044,28 @@ def int_hexagon_V6_vand_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vand_128B">; def int_hexagon_V6_vandqrt : -Hexagon_custom_v16i32_v64i1i32_Intrinsic; +Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt">; def int_hexagon_V6_vandqrt_128B : -Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; +Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_128B">; def int_hexagon_V6_vandqrt_acc : -Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; +Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc">; def int_hexagon_V6_vandqrt_acc_128B : -Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; +Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandqrt_acc_128B">; def int_hexagon_V6_vandvrt : -Hexagon_custom_v64i1_v16i32i32_Intrinsic; +Hexagon_v64i1_v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt">; def int_hexagon_V6_vandvrt_128B : -Hexagon_custom_v128i1_v32i32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_128B">; def int_hexagon_V6_vandvrt_acc : -Hexagon_custom_v64i1_v64i1v16i32i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc">; def int_hexagon_V6_vandvrt_acc_128B : -Hexagon_custom_v128i1_v128i1v32i32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32i32_Intrinsic<"HEXAGON_V6_vandvrt_acc_128B">; def int_hexagon_V6_vaslh : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vaslh">; @@ -4439,220 +4404,220 @@ def int_hexagon_V6_vdsaduh_acc_128B : Hexagon_v64i32_v64i32v64i32i32_Intrinsic<"HEXAGON_V6_vdsaduh_acc_128B">; def int_hexagon_V6_veqb : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb">; def int_hexagon_V6_veqb_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_128B">; def int_hexagon_V6_veqb_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_and">; def int_hexagon_V6_veqb_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_and_128B">; def int_hexagon_V6_veqb_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_or">; def int_hexagon_V6_veqb_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_or_128B">; def int_hexagon_V6_veqb_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqb_xor">; def int_hexagon_V6_veqb_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqb_xor_128B">; def int_hexagon_V6_veqh : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh">; def int_hexagon_V6_veqh_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_128B">; def int_hexagon_V6_veqh_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_and">; def int_hexagon_V6_veqh_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_and_128B">; def int_hexagon_V6_veqh_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_or">; def int_hexagon_V6_veqh_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_or_128B">; def int_hexagon_V6_veqh_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqh_xor">; def int_hexagon_V6_veqh_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqh_xor_128B">; def int_hexagon_V6_veqw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw">; def int_hexagon_V6_veqw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_128B">; def int_hexagon_V6_veqw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_and">; def int_hexagon_V6_veqw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_and_128B">; def int_hexagon_V6_veqw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_or">; def int_hexagon_V6_veqw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_or_128B">; def int_hexagon_V6_veqw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_veqw_xor">; def int_hexagon_V6_veqw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_veqw_xor_128B">; def int_hexagon_V6_vgtb : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb">; def int_hexagon_V6_vgtb_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_128B">; def int_hexagon_V6_vgtb_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_and">; def int_hexagon_V6_vgtb_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_and_128B">; def int_hexagon_V6_vgtb_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_or">; def int_hexagon_V6_vgtb_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_or_128B">; def int_hexagon_V6_vgtb_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtb_xor">; def int_hexagon_V6_vgtb_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtb_xor_128B">; def int_hexagon_V6_vgth : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth">; def int_hexagon_V6_vgth_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_128B">; def int_hexagon_V6_vgth_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_and">; def int_hexagon_V6_vgth_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_and_128B">; def int_hexagon_V6_vgth_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_or">; def int_hexagon_V6_vgth_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_or_128B">; def int_hexagon_V6_vgth_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgth_xor">; def int_hexagon_V6_vgth_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgth_xor_128B">; def int_hexagon_V6_vgtub : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub">; def int_hexagon_V6_vgtub_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_128B">; def int_hexagon_V6_vgtub_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_and">; def int_hexagon_V6_vgtub_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_and_128B">; def int_hexagon_V6_vgtub_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_or">; def int_hexagon_V6_vgtub_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_or_128B">; def int_hexagon_V6_vgtub_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtub_xor">; def int_hexagon_V6_vgtub_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtub_xor_128B">; def int_hexagon_V6_vgtuh : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh">; def int_hexagon_V6_vgtuh_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_128B">; def int_hexagon_V6_vgtuh_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_and">; def int_hexagon_V6_vgtuh_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_and_128B">; def int_hexagon_V6_vgtuh_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_or">; def int_hexagon_V6_vgtuh_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_or_128B">; def int_hexagon_V6_vgtuh_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuh_xor">; def int_hexagon_V6_vgtuh_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuh_xor_128B">; def int_hexagon_V6_vgtuw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw">; def int_hexagon_V6_vgtuw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_128B">; def int_hexagon_V6_vgtuw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_and">; def int_hexagon_V6_vgtuw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_and_128B">; def int_hexagon_V6_vgtuw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_or">; def int_hexagon_V6_vgtuw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_or_128B">; def int_hexagon_V6_vgtuw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtuw_xor">; def int_hexagon_V6_vgtuw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtuw_xor_128B">; def int_hexagon_V6_vgtw : -Hexagon_custom_v64i1_v16i32v16i32_Intrinsic; +Hexagon_v64i1_v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw">; def int_hexagon_V6_vgtw_128B : -Hexagon_custom_v128i1_v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_128B">; def int_hexagon_V6_vgtw_and : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_and">; def int_hexagon_V6_vgtw_and_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_and_128B">; def int_hexagon_V6_vgtw_or : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_or">; def int_hexagon_V6_vgtw_or_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_or_128B">; def int_hexagon_V6_vgtw_xor : -Hexagon_custom_v64i1_v64i1v16i32v16i32_Intrinsic; +Hexagon_v64i1_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vgtw_xor">; def int_hexagon_V6_vgtw_xor_128B : -Hexagon_custom_v128i1_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v128i1_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vgtw_xor_128B">; def int_hexagon_V6_vinsertwr : Hexagon_v16i32_v16i32i32_Intrinsic<"HEXAGON_V6_vinsertwr">; @@ -5051,10 +5016,10 @@ def int_hexagon_V6_vmpyuhv_acc_128B : Hexagon_v64i32_v64i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vmpyuhv_acc_128B">; def int_hexagon_V6_vmux : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vmux">; def int_hexagon_V6_vmux_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vmux_128B">; def int_hexagon_V6_vnavgh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vnavgh">; @@ -5375,16 +5340,16 @@ def int_hexagon_V6_vsubb_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubb_dv_128B">; def int_hexagon_V6_vsubbnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbnq">; def int_hexagon_V6_vsubbnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbnq_128B">; def int_hexagon_V6_vsubbq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubbq">; def int_hexagon_V6_vsubbq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubbq_128B">; def int_hexagon_V6_vsubh : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubh">; @@ -5399,16 +5364,16 @@ def int_hexagon_V6_vsubh_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubh_dv_128B">; def int_hexagon_V6_vsubhnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhnq">; def int_hexagon_V6_vsubhnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhnq_128B">; def int_hexagon_V6_vsubhq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhq">; def int_hexagon_V6_vsubhq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubhq_128B">; def int_hexagon_V6_vsubhsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubhsat">; @@ -5477,16 +5442,16 @@ def int_hexagon_V6_vsubw_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubw_dv_128B">; def int_hexagon_V6_vsubwnq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwnq">; def int_hexagon_V6_vsubwnq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwnq_128B">; def int_hexagon_V6_vsubwq : -Hexagon_custom_v16i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwq">; def int_hexagon_V6_vsubwq_128B : -Hexagon_custom_v32i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vsubwq_128B">; def int_hexagon_V6_vsubwsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vsubwsat">; @@ -5501,10 +5466,10 @@ def int_hexagon_V6_vsubwsat_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vsubwsat_dv_128B">; def int_hexagon_V6_vswap : -Hexagon_custom_v32i32_v64i1v16i32v16i32_Intrinsic; +Hexagon_v32i32_v64i1v16i32v16i32_Intrinsic<"HEXAGON_V6_vswap">; def int_hexagon_V6_vswap_128B : -Hexagon_custom_v64i32_v128i1v32i32v32i32_Intrinsic_128B; +Hexagon_v64i32_v128i1v32i32v32i32_Intrinsic<"HEXAGON_V6_vswap_128B">; def int_hexagon_V6_vtmpyb : Hexagon_v32i32_v32i32i32_Intrinsic<"HEXAGON_V6_vtmpyb">; @@ -5611,22 +5576,22 @@ def int_hexagon_V6_lvsplath_128B : Hexagon_v32i32_i32_Intrinsic<"HEXAGON_V6_lvsplath_128B">; def int_hexagon_V6_pred_scalar2v2 : -Hexagon_custom_v64i1_i32_Intrinsic; +Hexagon_v64i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2">; def int_hexagon_V6_pred_scalar2v2_128B : -Hexagon_custom_v128i1_i32_Intrinsic_128B; +Hexagon_v128i1_i32_Intrinsic<"HEXAGON_V6_pred_scalar2v2_128B">; def int_hexagon_V6_shuffeqh : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqh">; def int_hexagon_V6_shuffeqh_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqh_128B">; def int_hexagon_V6_shuffeqw : -Hexagon_custom_v64i1_v64i1v64i1_Intrinsic; +Hexagon_v64i1_v64i1v64i1_Intrinsic<"HEXAGON_V6_shuffeqw">; def int_hexagon_V6_shuffeqw_128B : -Hexagon_custom_v128i1_v128i1v128i1_Intrinsic_128B; +Hexagon_v128i1_v128i1v128i1_Intrinsic<"HEXAGON_V6_shuffeqw_128B">; def int_hexagon_V6_vaddbsat : Hexagon_v16i32_v16i32v16i32_Intrinsic<"HEXAGON_V6_vaddbsat">; @@ -5695,28 +5660,28 @@ def int_hexagon_V6_vadduwsat_dv_128B : Hexagon_v64i32_v64i32v64i32_Intrinsic<"HEXAGON_V6_vadduwsat_dv_128B">; def int_hexagon_V6_vandnqrt : -Hexagon_custom_v16i32_v64i1i32_Intrinsic; +Hexagon_v16i32_v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt">; def int_hexagon_V6_vandnqrt_128B : -Hexagon_custom_v32i32_v128i1i32_Intrinsic_128B; +Hexagon_v32i32_v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_128B">; def int_hexagon_V6_vandnqrt_acc : -Hexagon_custom_v16i32_v16i32v64i1i32_Intrinsic; +Hexagon_v16i32_v16i32v64i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc">; def int_hexagon_V6_vandnqrt_acc_128B : -Hexagon_custom_v32i32_v32i32v128i1i32_Intrinsic_128B; +Hexagon_v32i32_v32i32v128i1i32_Intrinsic<"HEXAGON_V6_vandnqrt_acc_128B">; def int_hexagon_V6_vandvnqv : -Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvnqv">; def int_hexagon_V6_vandvnqv_128B : -Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvnqv_128B">; def int_hexagon_V6_vandvqv : -Hexagon_custom_v16i32_v64i1v16i32_Intrinsic; +Hexagon_v16i32_v64i1v16i32_Intrinsic<"HEXAGON_V6_vandvqv">; def int_hexagon_V6_vandvqv_128B : -Hexagon_custom_v32i32_v128i1v32i32_Intrinsic_128B; +Hexagon_v32i32_v128i1v32i32_Intrinsic<"HEXAGON_V6_vandvqv_128B">; def int_hexagon_V6_vasrhbsat : Hexagon_v16i32_v16i32v16i32i32_Intrinsic<"HEXAGON_V6_vasrhbsat">; @@ -5961,10 +5926,10 @@ def int_hexagon_V6_vgathermh_128B : Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermh_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermhq : -Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; +Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermhq", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermhq_128B : -Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; +Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhq_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermhw : Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhw", [IntrArgMemOnly]>; @@ -5973,10 +5938,10 @@ def int_hexagon_V6_vgathermhw_128B : Hexagon__ptri32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhw_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermhwq : -Hexagon_custom__ptrv64i1i32i32v32i32_Intrinsic<[IntrArgMemOnly]>; +Hexagon__ptrv64i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermhwq", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermhwq_128B : -Hexagon_custom__ptrv128i1i32i32v64i32_Intrinsic_128B<[IntrArgMemOnly]>; +Hexagon__ptrv128i1i32i32v64i32_Intrinsic<"HEXAGON_V6_vgathermhwq_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermw : Hexagon__ptri32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermw", [IntrArgMemOnly]>; @@ -5985,10 +5950,10 @@ def int_hexagon_V6_vgathermw_128B : Hexagon__ptri32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermw_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermwq : -Hexagon_custom__ptrv64i1i32i32v16i32_Intrinsic<[IntrArgMemOnly]>; +Hexagon__ptrv64i1i32i32v16i32_Intrinsic<"HEXAGON_V6_vgathermwq", [IntrArgMemOnly]>; def int_hexagon_V6_vgathermwq_128B : -Hexagon_custom__ptrv128i1i32i32v32i32_Intrinsic_128B<[IntrArgMemOnly]>; +Hexagon__ptrv128i1i32i32v32i32_Intrinsic<"HEXAGON_V6_vgathermwq_128B", [IntrArgMemOnly]>; def int_hexagon_V6_vlut4 : Hexagon_v16i32_v16i32i64_Intrinsic<"HEXAGON_V6_vlut4">; @@ -6051,22 +6016,22 @@ def int_hexagon_V6_vnavgb_128B : Hexagon_v32i32_v32i32v32i32_Intrinsic<"HEXAGON_V6_vnavgb_128B">; def int_hexagon_V6_vprefixqb : -Hexagon_custom_v16i32_v64i1_Intrinsic; +Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqb">; def int_hexagon_V6_vprefixqb_128B : -Hexagon_custom_v32i32_v128i1_Intrinsic_128B; +Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqb_128B">; def int_hexagon_V6_vprefixqh : -Hexagon_custom_v16i32_v64i1_Intrinsic; +Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqh">; def int_hexagon_V6_vprefixqh_128B : -Hexagon_custom_v32i32_v128i1_Intrinsic_128B; +Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqh_128B">; def int_hexagon_V6_vprefixqw : -Hexagon_custom_v16i32_v64i1_Intrinsic; +Hexagon_v16i32_v64i1_Intrinsic<"HEXAGON_V6_vprefixqw">; def int_hexagon_V6_vprefixqw_128B : -Hexagon_custom_v32i32_v128i1_Intrinsic_128B; +Hexagon_v32i32_v128i1_Intrinsic<"HEXAGON_V6_vprefixqw_128B">; def int_hexagon_V6_vscattermh : Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermh", [IntrWriteMem]>; @@ -6081,10 +6046,10 @@ def int_hexagon_V6_vscattermh_add_128B : Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermh_add_128B", [IntrWriteMem]>; def int_hexagon_V6_vscattermhq : -Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhq", [IntrWriteMem]>; def int_hexagon_V6_vscattermhq_128B : -Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhq_128B", [IntrWriteMem]>; def int_hexagon_V6_vscattermhw : Hexagon__i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhw", [IntrWriteMem]>; @@ -6099,10 +6064,10 @@ def int_hexagon_V6_vscattermhw_add_128B : Hexagon__i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhw_add_128B", [IntrWriteMem]>; def int_hexagon_V6_vscattermhwq : -Hexagon_custom__v64i1i32i32v32i32v16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1i32i32v32i32v16i32_Intrinsic<"HEXAGON_V6_vscattermhwq", [IntrWriteMem]>; def int_hexagon_V6_vscattermhwq_128B : -Hexagon_custom__v128i1i32i32v64i32v32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1i32i32v64i32v32i32_Intrinsic<"HEXAGON_V6_vscattermhwq_128B", [IntrWriteMem]>; def int_hexagon_V6_vscattermw : Hexagon__i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermw", [IntrWriteMem]>; @@ -6117,18 +6082,18 @@ def int_hexagon_V6_vscattermw_add_128B : Hexagon__i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermw_add_128B", [IntrWriteMem]>; def int_hexagon_V6_vscattermwq : -Hexagon_custom__v64i1i32i32v16i32v16i32_Intrinsic<[IntrWriteMem]>; +Hexagon__v64i1i32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vscattermwq", [IntrWriteMem]>; def int_hexagon_V6_vscattermwq_128B : -Hexagon_custom__v128i1i32i32v32i32v32i32_Intrinsic_128B<[IntrWriteMem]>; +Hexagon__v128i1i32i32v32i32v32i32_Intrinsic<"HEXAGON_V6_vscattermwq_128B", [IntrWriteMem]>; // V66 HVX Instructions. def int_hexagon_V6_vaddcarrysat : -Hexagon_custom_v16i32_v16i32v16i32v64i1_Intrinsic; +Hexagon_v16i32_v16i32v16i32v64i1_Intrinsic<"HEXAGON_V6_vaddcarrysat">; def int_hexagon_V6_vaddcarrysat_128B : -Hexagon_custom_v32i32_v32i32v32i32v128i1_Intrinsic_128B; +Hexagon_v32i32_v32i32v32i32v128i1_Intrinsic<"HEXAGON_V6_vaddcarrysat_128B">; def int_hexagon_V6_vasr_into : Hexagon_v32i32_v32i32v16i32v16i32_Intrinsic<"HEXAGON_V6_vasr_into">;