forked from OSchip/llvm-project
[MIR] MIRNamer pass for improving MIR test authoring experience.
This patch reuses the MIR vreg renamer from the MIRCanonicalizerPass to cleanup names of vregs in a MIR file for MIR test authors. I found it useful when writing a regression test for a globalisel failure I encountered recently and thought it might be useful for other folks as well. Differential Revision: https://reviews.llvm.org/D67209 llvm-svn: 371121
This commit is contained in:
Puyan Lotfi
parent
bf7602b261
commit
dc97ca9f25
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@ -252,6 +252,7 @@ void initializeLowerInvokeLegacyPassPass(PassRegistry&);
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void initializeLowerSwitchPass(PassRegistry&);
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void initializeLowerTypeTestsPass(PassRegistry&);
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void initializeMIRCanonicalizerPass(PassRegistry &);
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void initializeMIRNamerPass(PassRegistry &);
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void initializeMIRPrintingPassPass(PassRegistry&);
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void initializeMachineBlockFrequencyInfoPass(PassRegistry&);
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void initializeMachineBlockPlacementPass(PassRegistry&);
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@ -122,6 +122,7 @@ add_llvm_library(LLVMCodeGen
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RegisterScavenging.cpp
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RenameIndependentSubregs.cpp
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MIRVRegNamerUtils.cpp
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MIRNamerPass.cpp
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MIRCanonicalizerPass.cpp
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RegisterUsageInfo.cpp
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RegUsageInfoCollector.cpp
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@ -54,6 +54,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
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initializeLocalStackSlotPassPass(Registry);
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initializeLowerIntrinsicsPass(Registry);
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initializeMIRCanonicalizerPass(Registry);
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initializeMIRNamerPass(Registry);
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initializeMachineBlockFrequencyInfoPass(Registry);
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initializeMachineBlockPlacementPass(Registry);
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initializeMachineBlockPlacementStatsPass(Registry);
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@ -0,0 +1,77 @@
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//===----------------------- MIRNamer.cpp - MIR Namer ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// The purpose of this pass is to rename virtual register operands with the goal
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// of making it easier to author easier to read tests for MIR. This pass reuses
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// the vreg renamer used by MIRCanonicalizerPass.
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//
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// Basic Usage:
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//
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// llc -o - -run-pass mir-namer example.mir
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//
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//===----------------------------------------------------------------------===//
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#include "MIRVRegNamerUtils.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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namespace llvm {
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extern char &MIRNamerID;
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} // namespace llvm
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#define DEBUG_TYPE "mir-namer"
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namespace {
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class MIRNamer : public MachineFunctionPass {
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public:
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static char ID;
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MIRNamer() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override {
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return "Rename virtual register operands";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool runOnMachineFunction(MachineFunction &MF) override {
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bool Changed = false;
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if (MF.empty())
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return Changed;
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NamedVRegCursor NVC(MF.getRegInfo());
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ReversePostOrderTraversal<MachineBasicBlock *> RPOT(&*MF.begin());
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for (auto &MBB : RPOT)
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Changed |= NVC.renameVRegs(MBB);
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return Changed;
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}
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};
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} // end anonymous namespace
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char MIRNamer::ID;
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char &llvm::MIRNamerID = MIRNamer::ID;
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INITIALIZE_PASS_BEGIN(MIRNamer, "mir-namer", "Rename Register Operands", false,
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false)
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INITIALIZE_PASS_END(MIRNamer, "mir-namer", "Rename Register Operands", false,
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false)
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@ -0,0 +1,90 @@
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# RUN: llc -mtriple aarch64-apple-ios -run-pass mir-namer -verify-machineinstrs -o - %s | FileCheck %s
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---
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name: foo
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body: |
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bb.0:
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;CHECK: bb
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;CHECK-NEXT: %namedVReg1353:_(p0) = COPY $d0
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;CHECK-NEXT: %namedVReg1352:_(<4 x s32>) = COPY $q0
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;CHECK-NEXT: G_STORE %namedVReg1352(<4 x s32>), %namedVReg1353
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liveins: $q0, $d0
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%1:fpr(p0) = COPY $d0
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%0:fpr(<4 x s32>) = COPY $q0
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G_STORE %0(<4 x s32>), %1(p0) :: (store 16)
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...
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---
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name: bar
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -4, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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;CHECK: bb
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;CHECK-NEXT: %namedVReg1370:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1371:gpr32 = MOVi32imm 1
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;CHECK-NEXT: %namedVReg1372:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1373:gpr32 = MOVi32imm 2
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;CHECK-NEXT: %namedVReg1359:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1360:gpr32 = MOVi32imm 3
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;CHECK-NEXT: %namedVReg1365:gpr32 = nsw ADDWrr
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;CHECK-NEXT: %namedVReg1361:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1366:gpr32 = nsw ADDWrr
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;CHECK-NEXT: %namedVReg1362:gpr32 = MOVi32imm 4
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;CHECK-NEXT: %namedVReg1355:gpr32 = nsw ADDWrr
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;CHECK-NEXT: %namedVReg1363:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1364:gpr32 = MOVi32imm 5
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%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%1:gpr32 = MOVi32imm 1
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%2:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%3:gpr32 = MOVi32imm 2
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%4:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%5:gpr32 = MOVi32imm 3
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%10:gpr32 = nsw ADDWrr %0:gpr32, %1:gpr32
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%6:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%11:gpr32 = nsw ADDWrr %2:gpr32, %3:gpr32
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%7:gpr32 = MOVi32imm 4
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%12:gpr32 = nsw ADDWrr %4:gpr32, %5:gpr32
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%8:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%9:gpr32 = MOVi32imm 5
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%13:gpr32 = nsw ADDWrr %6:gpr32, %7:gpr32
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%14:gpr32 = nsw ADDWrr %8:gpr32, %9:gpr32
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%15:gpr32 = nsw ADDWrr %10:gpr32, %11:gpr32
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%16:gpr32 = nsw ADDWrr %12:gpr32, %13:gpr32
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%17:gpr32 = nsw ADDWrr %14:gpr32, %15:gpr32
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%18:gpr32 = nsw ADDWrr %16:gpr32, %17:gpr32
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$w0 = COPY %18
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RET_ReallyLR implicit $w0
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...
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---
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name: baz
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '', callee-saved-restored: true,
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local-offset: -4, debug-info-variable: '', debug-info-expression: '',
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debug-info-location: '' }
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body: |
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bb.0:
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liveins: $x0, $x1, $d0, $d1
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;CHECK: bb
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;CHECK-NEXT: %namedVReg1355:gpr32 = LDRWui
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;CHECK-NEXT: %namedVReg1354:gpr32 = COPY %namedVReg1355
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;CHECK-NEXT: %namedVReg1353:gpr32 = COPY %namedVReg1354
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;CHECK-NEXT: %namedVReg1352:gpr32 = COPY %namedVReg1353
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;CHECK-NEXT: $w0 = COPY %namedVReg1352
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%0:gpr32 = LDRWui %stack.0, 0 :: (dereferenceable load 8)
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%1:gpr32 = COPY %0
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%2:gpr32 = COPY %1
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%3:gpr32 = COPY %2
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$w0 = COPY %3
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RET_ReallyLR implicit $w0
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...
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