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Autogenerate a couple of test in the AMDGPU backend. NFC

This commit is contained in:
Amaury Séchet 2022-09-25 14:00:22 +00:00
parent 196f27bb56
commit dc947ba3f5
2 changed files with 147 additions and 74 deletions
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106
llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_1op.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s
declare i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half)
@ -26,7 +27,8 @@ declare half @llvm.aarch64.neon.frecpe.f16(half)
define dso_local i16 @t2(half %a) {
; CHECK-LABEL: t2:
; CHECK: fcmp h0, #0.0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, #0.0
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: ret
entry:
@ -37,7 +39,8 @@ entry:
define dso_local i16 @t3(half %a) {
; CHECK-LABEL: t3:
; CHECK: fcmp h0, #0.0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, #0.0
; CHECK-NEXT: csetm w0, ge
; CHECK-NEXT: ret
entry:
@ -48,7 +51,8 @@ entry:
define dso_local i16 @t4(half %a) {
; CHECK-LABEL: t4:
; CHECK: fcmp h0, #0.0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, #0.0
; CHECK-NEXT: csetm w0, gt
; CHECK-NEXT: ret
entry:
@ -59,7 +63,8 @@ entry:
define dso_local i16 @t5(half %a) {
; CHECK-LABEL: t5:
; CHECK: fcmp h0, #0.0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, #0.0
; CHECK-NEXT: csetm w0, ls
; CHECK-NEXT: ret
entry:
@ -70,7 +75,8 @@ entry:
define dso_local i16 @t6(half %a) {
; CHECK-LABEL: t6:
; CHECK: fcmp h0, #0.0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, #0.0
; CHECK-NEXT: csetm w0, mi
; CHECK-NEXT: ret
entry:
@ -81,7 +87,8 @@ entry:
define dso_local half @t8(i32 %a) {
; CHECK-LABEL: t8:
; CHECK: scvtf h0, w0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf h0, w0
; CHECK-NEXT: ret
entry:
%0 = sitofp i32 %a to half
@ -90,7 +97,8 @@ entry:
define dso_local half @t9(i64 %a) {
; CHECK-LABEL: t9:
; CHECK: scvtf h0, x0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: scvtf h0, x0
; CHECK-NEXT: ret
entry:
%0 = sitofp i64 %a to half
@ -99,7 +107,8 @@ entry:
define dso_local half @t12(i64 %a) {
; CHECK-LABEL: t12:
; CHECK: ucvtf h0, x0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ucvtf h0, x0
; CHECK-NEXT: ret
entry:
%0 = uitofp i64 %a to half
@ -108,7 +117,8 @@ entry:
define dso_local i16 @t13(half %a) {
; CHECK-LABEL: t13:
; CHECK: fcvtzs w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
entry:
%0 = fptosi half %a to i16
@ -117,7 +127,8 @@ entry:
define dso_local i64 @t15(half %a) {
; CHECK-LABEL: t15:
; CHECK: fcvtzs x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs x0, h0
; CHECK-NEXT: ret
entry:
%0 = fptosi half %a to i64
@ -126,7 +137,8 @@ entry:
define dso_local i16 @t16(half %a) {
; CHECK-LABEL: t16:
; CHECK: fcvtzs w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
entry:
%0 = fptoui half %a to i16
@ -135,7 +147,8 @@ entry:
define dso_local i64 @t18(half %a) {
; CHECK-LABEL: t18:
; CHECK: fcvtzu x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu x0, h0
; CHECK-NEXT: ret
entry:
%0 = fptoui half %a to i64
@ -144,7 +157,8 @@ entry:
define i32 @fcvtzu_intrinsic_i32(half %a) {
; CHECK-LABEL: fcvtzu_intrinsic_i32:
; CHECK: fcvtzu w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtzu.i32.f16(half %a)
@ -153,7 +167,8 @@ entry:
define i64 @fcvtzu_intrinsic_i64(half %a) {
; CHECK-LABEL: fcvtzu_intrinsic_i64:
; CHECK: fcvtzs x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs x0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
@ -162,7 +177,8 @@ entry:
define i32 @fcvtzs_intrinsic_i32(half %a) {
; CHECK-LABEL: fcvtzs_intrinsic_i32:
; CHECK: fcvtzs w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtzs.i32.f16(half %a)
@ -171,7 +187,8 @@ entry:
define i64 @fcvtzs_intrinsic_i64(half %a) {
; CHECK-LABEL: fcvtzs_intrinsic_i64:
; CHECK: fcvtzs x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs x0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i64 @llvm.aarch64.neon.fcvtzs.i64.f16(half %a)
@ -180,7 +197,8 @@ entry:
define dso_local i16 @t19(half %a) {
; CHECK-LABEL: t19:
; CHECK: fcvtas w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtas w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtas.i32.f16(half %a)
@ -190,7 +208,8 @@ entry:
define dso_local i64 @t21(half %a) {
; CHECK-LABEL: t21:
; CHECK: fcvtas x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtas x0, h0
; CHECK-NEXT: ret
entry:
%vcvtah_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtas.i64.f16(half %a)
@ -199,7 +218,8 @@ entry:
define dso_local i16 @t22(half %a) {
; CHECK-LABEL: t22:
; CHECK: fcvtau w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtau w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtau.i32.f16(half %a)
@ -209,7 +229,8 @@ entry:
define dso_local i64 @t24(half %a) {
; CHECK-LABEL: t24:
; CHECK: fcvtau x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtau x0, h0
; CHECK-NEXT: ret
entry:
%vcvtah_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtau.i64.f16(half %a)
@ -218,7 +239,8 @@ entry:
define dso_local i16 @t25(half %a) {
; CHECK-LABEL: t25:
; CHECK: fcvtms w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtms w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtms.i32.f16(half %a)
@ -228,7 +250,8 @@ entry:
define dso_local i64 @t27(half %a) {
; CHECK-LABEL: t27:
; CHECK: fcvtms x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtms x0, h0
; CHECK-NEXT: ret
entry:
%vcvtmh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtms.i64.f16(half %a)
@ -237,7 +260,8 @@ entry:
define dso_local i16 @t28(half %a) {
; CHECK-LABEL: t28:
; CHECK: fcvtmu w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtmu w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtmu.i32.f16(half %a)
@ -247,7 +271,8 @@ entry:
define dso_local i64 @t30(half %a) {
; CHECK-LABEL: t30:
; CHECK: fcvtmu x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtmu x0, h0
; CHECK-NEXT: ret
entry:
%vcvtmh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtmu.i64.f16(half %a)
@ -256,7 +281,8 @@ entry:
define dso_local i16 @t31(half %a) {
; CHECK-LABEL: t31:
; CHECK: fcvtns w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtns w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtns.i32.f16(half %a)
@ -266,7 +292,8 @@ entry:
define dso_local i64 @t33(half %a) {
; CHECK-LABEL: t33:
; CHECK: fcvtns x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtns x0, h0
; CHECK-NEXT: ret
entry:
%vcvtnh_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtns.i64.f16(half %a)
@ -275,7 +302,8 @@ entry:
define dso_local i16 @t34(half %a) {
; CHECK-LABEL: t34:
; CHECK: fcvtnu w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtnu w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtnu.i32.f16(half %a)
@ -285,7 +313,8 @@ entry:
define dso_local i64 @t36(half %a) {
; CHECK-LABEL: t36:
; CHECK: fcvtnu x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtnu x0, h0
; CHECK-NEXT: ret
entry:
%vcvtnh_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtnu.i64.f16(half %a)
@ -294,7 +323,8 @@ entry:
define dso_local i16 @t37(half %a) {
; CHECK-LABEL: t37:
; CHECK: fcvtps w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtps w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtps.i32.f16(half %a)
@ -304,7 +334,8 @@ entry:
define dso_local i64 @t39(half %a) {
; CHECK-LABEL: t39:
; CHECK: fcvtps x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtps x0, h0
; CHECK-NEXT: ret
entry:
%vcvtph_s64_f16 = tail call i64 @llvm.aarch64.neon.fcvtps.i64.f16(half %a)
@ -313,7 +344,8 @@ entry:
define dso_local i16 @t40(half %a) {
; CHECK-LABEL: t40:
; CHECK: fcvtpu w0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtpu w0, h0
; CHECK-NEXT: ret
entry:
%fcvt = tail call i32 @llvm.aarch64.neon.fcvtpu.i32.f16(half %a)
@ -323,7 +355,8 @@ entry:
define dso_local i64 @t42(half %a) {
; CHECK-LABEL: t42:
; CHECK: fcvtpu x0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtpu x0, h0
; CHECK-NEXT: ret
entry:
%vcvtph_u64_f16 = tail call i64 @llvm.aarch64.neon.fcvtpu.i64.f16(half %a)
@ -332,7 +365,8 @@ entry:
define dso_local half @t44(half %a) {
; CHECK-LABEL: t44:
; CHECK: frecpe h0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: frecpe h0, h0
; CHECK-NEXT: ret
entry:
%vrecpeh_f16 = tail call half @llvm.aarch64.neon.frecpe.f16(half %a)
@ -341,7 +375,8 @@ entry:
define dso_local half @t45(half %a) {
; CHECK-LABEL: t45:
; CHECK: frecpx h0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: frecpx h0, h0
; CHECK-NEXT: ret
entry:
%vrecpxh_f16 = tail call half @llvm.aarch64.neon.frecpx.f16(half %a)
@ -350,7 +385,8 @@ entry:
define dso_local half @t53(half %a) {
; CHECK-LABEL: t53:
; CHECK: frsqrte h0, h0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: frsqrte h0, h0
; CHECK-NEXT: ret
entry:
%vrsqrteh_f16 = tail call half @llvm.aarch64.neon.frsqrte.f16(half %a)

115
llvm/test/CodeGen/AArch64/fp16_intrinsic_scalar_2op.ll
View File

@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-eabi -mattr=+v8.2a,+fullfp16 | FileCheck %s
declare half @llvm.aarch64.sisd.fabd.f16(half, half)
@ -12,7 +13,8 @@ declare i32 @llvm.aarch64.neon.facgt.i32.f16(half, half)
define dso_local half @t_vabdh_f16(half %a, half %b) {
; CHECK-LABEL: t_vabdh_f16:
; CHECK: fabd h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fabd h0, h0, h1
; CHECK-NEXT: ret
entry:
%vabdh_f16 = tail call half @llvm.aarch64.sisd.fabd.f16(half %a, half %b)
@ -21,7 +23,8 @@ entry:
define dso_local half @t_vabdh_f16_from_fsub_fabs(half %a, half %b) {
; CHECK-LABEL: t_vabdh_f16_from_fsub_fabs:
; CHECK: fabd h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fabd h0, h0, h1
; CHECK-NEXT: ret
entry:
%sub = fsub half %a, %b
@ -31,7 +34,8 @@ entry:
define dso_local i16 @t_vceqh_f16(half %a, half %b) {
; CHECK-LABEL: t_vceqh_f16:
; CHECK: fcmp h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, h1
; CHECK-NEXT: csetm w0, eq
; CHECK-NEXT: ret
entry:
@ -42,7 +46,8 @@ entry:
define dso_local i16 @t_vcgeh_f16(half %a, half %b) {
; CHECK-LABEL: t_vcgeh_f16:
; CHECK: fcmp h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, h1
; CHECK-NEXT: csetm w0, ge
; CHECK-NEXT: ret
entry:
@ -53,7 +58,8 @@ entry:
define dso_local i16 @t_vcgth_f16(half %a, half %b) {
; CHECK-LABEL: t_vcgth_f16:
; CHECK: fcmp h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, h1
; CHECK-NEXT: csetm w0, gt
; CHECK-NEXT: ret
entry:
@ -64,7 +70,8 @@ entry:
define dso_local i16 @t_vcleh_f16(half %a, half %b) {
; CHECK-LABEL: t_vcleh_f16:
; CHECK: fcmp h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, h1
; CHECK-NEXT: csetm w0, ls
; CHECK-NEXT: ret
entry:
@ -75,7 +82,8 @@ entry:
define dso_local i16 @t_vclth_f16(half %a, half %b) {
; CHECK-LABEL: t_vclth_f16:
; CHECK: fcmp h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcmp h0, h1
; CHECK-NEXT: csetm w0, mi
; CHECK-NEXT: ret
entry:
@ -86,7 +94,8 @@ entry:
define dso_local half @t_vmaxh_f16(half %a, half %b) {
; CHECK-LABEL: t_vmaxh_f16:
; CHECK: fmax h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmax h0, h0, h1
; CHECK-NEXT: ret
entry:
%vmax = tail call half @llvm.aarch64.neon.fmax.f16(half %a, half %b)
@ -95,7 +104,8 @@ entry:
define dso_local half @t_vminh_f16(half %a, half %b) {
; CHECK-LABEL: t_vminh_f16:
; CHECK: fmin h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmin h0, h0, h1
; CHECK-NEXT: ret
entry:
%vmin = tail call half @llvm.aarch64.neon.fmin.f16(half %a, half %b)
@ -104,7 +114,8 @@ entry:
define dso_local half @t_vmulxh_f16(half %a, half %b) {
; CHECK-LABEL: t_vmulxh_f16:
; CHECK: fmulx h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmulx h0, h0, h1
; CHECK-NEXT: ret
entry:
%vmulxh_f16 = tail call half @llvm.aarch64.neon.fmulx.f16(half %a, half %b)
@ -113,7 +124,8 @@ entry:
define dso_local half @t_vrecpsh_f16(half %a, half %b) {
; CHECK-LABEL: t_vrecpsh_f16:
; CHECK: frecps h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: frecps h0, h0, h1
; CHECK-NEXT: ret
entry:
%vrecps = tail call half @llvm.aarch64.neon.frecps.f16(half %a, half %b)
@ -122,7 +134,8 @@ entry:
define dso_local half @t_vrsqrtsh_f16(half %a, half %b) {
; CHECK-LABEL: t_vrsqrtsh_f16:
; CHECK: frsqrts h0, h0, h1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: frsqrts h0, h0, h1
; CHECK-NEXT: ret
entry:
%vrsqrtsh_f16 = tail call half @llvm.aarch64.neon.frsqrts.f16(half %a, half %b)
@ -138,7 +151,8 @@ declare i32 @llvm.aarch64.neon.vcvtfp2fxu.i32.f16(half, i32) #1
define dso_local half @test_vcvth_n_f16_s16_1(i16 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s16_1:
; CHECK: fmov s0, w[[wReg:[0-9]+]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: scvtf h0, h0, #1
; CHECK-NEXT: ret
entry:
@ -149,7 +163,8 @@ entry:
define dso_local half @test_vcvth_n_f16_s16_16(i16 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s16_16:
; CHECK: fmov s0, w[[wReg:[0-9]+]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: scvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
@ -160,7 +175,8 @@ entry:
define dso_local half @test_vcvth_n_f16_s32_1(i32 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s32_1:
; CHECK: fmov s0, w0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: scvtf h0, h0, #1
; CHECK-NEXT: ret
entry:
@ -170,7 +186,8 @@ entry:
define dso_local half @test_vcvth_n_f16_s32_16(i32 %a) {
; CHECK-LABEL: test_vcvth_n_f16_s32_16:
; CHECK: fmov s0, w0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: scvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
@ -180,7 +197,8 @@ entry:
define dso_local i16 @test_vcvth_n_s16_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_s16_f16_1:
; CHECK: fcvtzs h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -191,7 +209,8 @@ entry:
define dso_local i16 @test_vcvth_n_s16_f16_16(half %a) {
; CHECK-LABEL: test_vcvth_n_s16_f16_16:
; CHECK: fcvtzs h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #16
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -202,7 +221,8 @@ entry:
define dso_local i32 @test_vcvth_n_s32_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_s32_f16_1:
; CHECK: fcvtzs h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -212,7 +232,8 @@ entry:
define dso_local i32 @test_vcvth_n_s32_f16_16(half %a) {
; CHECK-LABEL: test_vcvth_n_s32_f16_16:
; CHECK: fcvtzs h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #16
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -222,7 +243,8 @@ entry:
define dso_local i64 @test_vcvth_n_s64_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_s64_f16_1:
; CHECK: fcvtzs h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #1
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
entry:
@ -232,7 +254,8 @@ entry:
define dso_local i64 @test_vcvth_n_s64_f16_32(half %a) {
; CHECK-LABEL: test_vcvth_n_s64_f16_32:
; CHECK: fcvtzs h0, h0, #32
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzs h0, h0, #32
; CHECK-NEXT: fmov x0, d0
; CHECK-NEXT: ret
entry:
@ -242,7 +265,9 @@ entry:
define dso_local half @test_vcvth_n_f16_u16_1(i16 %a) {
; CHECK-LABEL: test_vcvth_n_f16_u16_1:
; CHECK: ucvtf h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ucvtf h0, h0, #1
; CHECK-NEXT: ret
entry:
%0 = zext i16 %a to i32
@ -252,7 +277,9 @@ entry:
define dso_local half @test_vcvth_n_f16_u16_16(i16 %a) {
; CHECK-LABEL: test_vcvth_n_f16_u16_16:
; CHECK: ucvtf h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ucvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
%0 = zext i16 %a to i32
@ -262,7 +289,8 @@ entry:
define dso_local half @test_vcvth_n_f16_u32_1(i32 %a) {
; CHECK-LABEL: test_vcvth_n_f16_u32_1:
; CHECK: fmov s0, w0
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ucvtf h0, h0, #1
; CHECK-NEXT: ret
entry:
@ -272,7 +300,9 @@ entry:
define dso_local half @test_vcvth_n_f16_u32_16(i32 %a) {
; CHECK-LABEL: test_vcvth_n_f16_u32_16:
; CHECK: ucvtf h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov s0, w0
; CHECK-NEXT: ucvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
%vcvth_n_f16_u32 = tail call half @llvm.aarch64.neon.vcvtfxu2fp.f16.i32(i32 %a, i32 16)
@ -281,7 +311,8 @@ entry:
define dso_local i16 @test_vcvth_n_u16_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_u16_f16_1:
; CHECK: fcvtzu h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu h0, h0, #1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -292,7 +323,8 @@ entry:
define dso_local i16 @test_vcvth_n_u16_f16_16(half %a) {
; CHECK-LABEL: test_vcvth_n_u16_f16_16:
; CHECK: fcvtzu h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu h0, h0, #16
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -303,7 +335,8 @@ entry:
define dso_local i32 @test_vcvth_n_u32_f16_1(half %a) {
; CHECK-LABEL: test_vcvth_n_u32_f16_1:
; CHECK: fcvtzu h0, h0, #1
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu h0, h0, #1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -313,7 +346,8 @@ entry:
define dso_local i32 @test_vcvth_n_u32_f16_16(half %a) {
; CHECK-LABEL: test_vcvth_n_u32_f16_16:
; CHECK: fcvtzu h0, h0, #16
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fcvtzu h0, h0, #16
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
@ -323,9 +357,10 @@ entry:
define dso_local i16 @vcageh_f16_test(half %a, half %b) {
; CHECK-LABEL: vcageh_f16_test:
; CHECK: facge h0, h0, h1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: facge h0, h0, h1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%facg = tail call i32 @llvm.aarch64.neon.facge.i32.f16(half %a, half %b)
%0 = trunc i32 %facg to i16
@ -334,9 +369,10 @@ entry:
define dso_local i16 @vcagth_f16_test(half %a, half %b) {
; CHECK-LABEL: vcagth_f16_test:
; CHECK: facgt h0, h0, h1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: facgt h0, h0, h1
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ret
entry:
%facg = tail call i32 @llvm.aarch64.neon.facgt.i32.f16(half %a, half %b)
%0 = trunc i32 %facg to i16
@ -345,9 +381,10 @@ entry:
define dso_local half @vcvth_n_f16_s64_test(i64 %a) {
; CHECK-LABEL: vcvth_n_f16_s64_test:
; CHECK: fmov d0, x0
; CHECK-NEXT: scvtf h0, h0, #16
; CHECK-NEXT: ret
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: scvtf h0, h0, #16
; CHECK-NEXT: ret
entry:
%vcvth_n_f16_s64 = tail call half @llvm.aarch64.neon.vcvtfxs2fp.f16.i64(i64 %a, i32 16)
ret half %vcvth_n_f16_s64