forked from OSchip/llvm-project
Thumb disassembler was erroneously rejecting "blx sp" instruction.
rdar://problem/9267838 llvm-svn: 129320
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@ -369,6 +369,15 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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let Inst{2-0} = 0b000;
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}
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def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
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[/* for disassembly only */]>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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let Inst{2-0} = 0b000;
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}
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
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IIC_Br, "bx\t$Rm",
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@ -485,10 +485,13 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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return true;
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// BX/BLX has 1 reg operand: Rm.
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if (NumOps == 1) {
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if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
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// Handling the two predicate operands before the reg operand.
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if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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return false;
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MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
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getT1Rm(insn))));
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NumOpsAdded = 1;
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NumOpsAdded = 3;
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return true;
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}
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@ -214,3 +214,12 @@
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# CHECK: lsr.w r10, r0, #32
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0x4f 0xea 0x10 0x0a
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# CHECK: blx sp
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0xe8 0x47
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# CHECK: bx lr
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0x70 0x47
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# CHECK: bx pc
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0x78 0x47
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@ -1624,6 +1624,10 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
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if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
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return false;
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// A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg.
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if (Name == "tBX_RET" || Name == "tBX_RET_vararg")
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return false;
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// Ignore the TPsoft (TLS) instructions, which conflict with tBLr9.
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if (Name == "tTPsoft" || Name == "t2TPsoft")
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return false;
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