From dc69265eea888e8c6255aebcdd6650420dd00cfb Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" Date: Wed, 22 Jan 2020 15:45:42 +0100 Subject: [PATCH] [VE] setcc isel patterns Summary: SETCC isel patterns and tests for i32/64 and fp32/64 comparison Reviewers: arsenm, rengolin, craig.topper, k-ishizaka Reviewed By: arsenm Subscribers: merge_guards_bot, wdng, hiraditya, llvm-commits Tags: #ve, #llvm Differential Revision: https://reviews.llvm.org/D73171 --- llvm/lib/Target/VE/VEISelLowering.cpp | 2 +- llvm/lib/Target/VE/VEInstrInfo.td | 191 ++++++++++++++++++++++- llvm/test/CodeGen/VE/setccf32.ll | 187 +++++++++++++++++++++++ llvm/test/CodeGen/VE/setccf32i.ll | 211 ++++++++++++++++++++++++++ llvm/test/CodeGen/VE/setccf64.ll | 187 +++++++++++++++++++++++ llvm/test/CodeGen/VE/setccf64i.ll | 199 ++++++++++++++++++++++++ llvm/test/CodeGen/VE/setcci32.ll | 121 +++++++++++++++ llvm/test/CodeGen/VE/setcci32i.ll | 131 ++++++++++++++++ llvm/test/CodeGen/VE/setcci64.ll | 121 +++++++++++++++ llvm/test/CodeGen/VE/setcci64i.ll | 131 ++++++++++++++++ 10 files changed, 1479 insertions(+), 2 deletions(-) create mode 100644 llvm/test/CodeGen/VE/setccf32.ll create mode 100644 llvm/test/CodeGen/VE/setccf32i.ll create mode 100644 llvm/test/CodeGen/VE/setccf64.ll create mode 100644 llvm/test/CodeGen/VE/setccf64i.ll create mode 100644 llvm/test/CodeGen/VE/setcci32.ll create mode 100644 llvm/test/CodeGen/VE/setcci32i.ll create mode 100644 llvm/test/CodeGen/VE/setcci64.ll create mode 100644 llvm/test/CodeGen/VE/setcci64i.ll diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index 471d4c2c9ef8..46cbf57eb746 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -245,5 +245,5 @@ const char *VETargetLowering::getTargetNodeName(unsigned Opcode) const { EVT VETargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, EVT VT) const { - return MVT::i64; + return MVT::i32; } diff --git a/llvm/lib/Target/VE/VEInstrInfo.td b/llvm/lib/Target/VE/VEInstrInfo.td index 82b6b0dd8bad..9fb0a866f326 100644 --- a/llvm/lib/Target/VE/VEInstrInfo.td +++ b/llvm/lib/Target/VE/VEInstrInfo.td @@ -37,6 +37,26 @@ def fplomsbzero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() def fplozero : PatLeaf<(fpimm), [{ return (N->getValueAPF().bitcastToAPInt() .getZExtValue() & 0xffffffff) == 0; }]>; +def CCSIOp : PatLeaf<(cond), [{ + switch (N->get()) { + default: return true; + case ISD::SETULT: + case ISD::SETULE: + case ISD::SETUGT: + case ISD::SETUGE: return false; + } +}]>; + +def CCUIOp : PatLeaf<(cond), [{ + switch (N->get()) { + default: return true; + case ISD::SETLT: + case ISD::SETLE: + case ISD::SETGT: + case ISD::SETGE: return false; + } +}]>; + def LOFP32 : SDNodeXFormgetValueAPF().bitcastToAPInt(); @@ -62,6 +82,54 @@ def HI32 : SDNodeXForm; +def icond2cc : SDNodeXFormget()) { + default: llvm_unreachable("Unknown integer condition code!"); + case ISD::SETEQ: cc = VECC::CC_IEQ; break; + case ISD::SETNE: cc = VECC::CC_INE; break; + case ISD::SETLT: cc = VECC::CC_IL; break; + case ISD::SETGT: cc = VECC::CC_IG; break; + case ISD::SETLE: cc = VECC::CC_ILE; break; + case ISD::SETGE: cc = VECC::CC_IGE; break; + case ISD::SETULT: cc = VECC::CC_IL; break; + case ISD::SETULE: cc = VECC::CC_ILE; break; + case ISD::SETUGT: cc = VECC::CC_IG; break; + case ISD::SETUGE: cc = VECC::CC_IGE; break; + } + return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); +}]>; + +def fcond2cc : SDNodeXFormget()) { + default: llvm_unreachable("Unknown float condition code!"); + case ISD::SETFALSE: cc = VECC::CC_AF; break; + case ISD::SETEQ: + case ISD::SETOEQ: cc = VECC::CC_EQ; break; + case ISD::SETNE: + case ISD::SETONE: cc = VECC::CC_NE; break; + case ISD::SETLT: + case ISD::SETOLT: cc = VECC::CC_L; break; + case ISD::SETGT: + case ISD::SETOGT: cc = VECC::CC_G; break; + case ISD::SETLE: + case ISD::SETOLE: cc = VECC::CC_LE; break; + case ISD::SETGE: + case ISD::SETOGE: cc = VECC::CC_GE; break; + case ISD::SETO: cc = VECC::CC_NUM; break; + case ISD::SETUO: cc = VECC::CC_NAN; break; + case ISD::SETUEQ: cc = VECC::CC_EQNAN; break; + case ISD::SETUNE: cc = VECC::CC_NENAN; break; + case ISD::SETULT: cc = VECC::CC_LNAN; break; + case ISD::SETUGT: cc = VECC::CC_GNAN; break; + case ISD::SETULE: cc = VECC::CC_LENAN; break; + case ISD::SETUGE: cc = VECC::CC_GENAN; break; + case ISD::SETTRUE: cc = VECC::CC_AT; break; + } + return CurDAG->getTargetConstant(cc, SDLoc(N), MVT::i32); +}]>; + // ASX format of memory address def MEMri : Operand { let PrintMethod = "printMemASXOperand"; @@ -195,6 +263,14 @@ multiclass RRmrropc, SDNode OpNode, { let cy = 1; let cz = 1; let hasSideEffects = 0; } } +multiclass RRNDmrropc, + RegisterClass RCo, ValueType Tyo, + RegisterClass RCi, ValueType Tyi> { + def rr : RR + { let cy = 1; let cz = 1; let hasSideEffects = 0; } +} + multiclass RRmriopc, SDNode OpNode, RegisterClass RCo, ValueType Tyo, RegisterClass RCi, ValueType Tyi, Operand immOp> { @@ -258,6 +334,18 @@ multiclass RRmopc, SDNode OpNode, RRNDmrm, RRNDmim; +// Used by cmp instruction +// The order of operands are "$sx, $sy, $sz" + +multiclass RRNDmopc, + RegisterClass RC, ValueType Ty, + Operand immOp, Operand immOp2> : + RRNDmrr, + //RRNDmir, + //RRNDmiz, + RRNDmrm, + RRNDmim; + // Multiclass for RR type instructions // Used by sra, sla, sll, and similar instructions // The order of operands are "$sx, $sz, $sy" @@ -274,6 +362,22 @@ multiclass RRImopc, SDNode OpNode, } } +// Multiclass for RR type instructions +// Used by cmov instruction + +let Constraints = "$sx = $sd", DisableEncoding = "$sd" in +multiclass RRCMOVmopc, + RegisterClass RC, ValueType Ty, Operand immOp, Operand immOp2> { + def rm0 : RR< + opc, (outs I64:$sx), (ins CCOp:$cf, RC:$sy, immOp2:$sz, I64:$sd), + !strconcat(opcStr, " $sx, (${sz})0, $sy")> { + let cy = 1; + let cz = 0; + let sz{6} = 1; + let hasSideEffects = 0; + } +} + // Branch multiclass let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in multiclass BCRm opc, @@ -292,6 +396,20 @@ multiclass BCRm opc, // Instructions //===----------------------------------------------------------------------===// +// CMOV instructions +let cx = 0, cw = 0, cw2 = 0 in +defm CMOVL : RRCMOVm<"cmov.l.${cf}", 0x3B, I64, i64, simm7Op64, uimm6Op64>; + +let cx = 0, cw = 1, cw2 = 0 in +defm CMOVW : RRCMOVm<"cmov.w.${cf}", 0x3B, I32, i32, simm7Op64, uimm6Op32>; + +let cx = 0, cw = 0, cw2 = 1 in +defm CMOVD : RRCMOVm<"cmov.d.${cf}", 0x3B, I64, f64, simm7Op64, uimm6Op64>; + +let cx = 0, cw = 1, cw2 = 1 in +defm CMOVS : RRCMOVm<"cmov.s.${cf}", 0x3B, F32, f32, simm7Op64, uimm6Op32>; + + // LEA and LEASL instruction (load 32 bit imm to low or high part) let cx = 0 in defm LEA : RMm<"lea", 0x06, I64, i64, simm7Op64, simm32Op64>; @@ -311,11 +429,27 @@ defm ADS : RRm<"adds.w.sx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; let cx = 1 in defm ADSU : RRm<"adds.w.zx", 0x4A, add, I32, i32, simm7Op32, uimm6Op32>; - // ADX instruction let cx = 0 in defm ADX : RRm<"adds.l", 0x59, add, I64, i64, simm7Op64, uimm6Op64>; +// CMP instruction +let cx = 0 in +defm CMP : RRNDm<"cmpu.l", 0x55, I64, i64, simm7Op64, uimm6Op64>; +let cx = 1 in +defm CMPUW : RRNDm<"cmpu.w", 0x55, I32, i32, simm7Op32, uimm6Op32>; + +// CPS instruction +let cx = 0 in +defm CPS : RRNDm<"cmps.w.sx", 0x7A, I32, i32, simm7Op32, uimm6Op32>; +let cx = 1 in +defm CPSU : RRNDm<"cmps.w.zx", 0x7A, I32, i32, simm7Op32, uimm6Op32>; + +// CPX instruction +let cx = 0 in +defm CPX : RRNDm<"cmps.l", 0x6A, I64, i64, simm7Op64, uimm6Op64>; + + // 5.3.2.3. Logical Arithmetic Operation Instructions let cx = 0 in { @@ -324,6 +458,7 @@ let cx = 0 in { let isCodeGenOnly = 1 in { defm AND32 : RRm<"and", 0x44, and, I32, i32, simm7Op32, uimm6Op32>; defm OR32 : RRm<"or", 0x45, or, I32, i32, simm7Op32, uimm6Op32>; + defm XOR32 : RRm<"xor", 0x46, xor, I32, i32, simm7Op32, uimm6Op32>; } } @@ -340,6 +475,11 @@ defm SLL : RRIm<"sll", 0x65, shl, I64, i64, simm7Op32, uimm6Op64>; let cx = 0 in defm SLA : RRIm<"sla.w.sx", 0x66, shl, I32, i32, simm7Op32, uimm6Op32>; +// FCP instruction +let cx = 0 in +defm FCP : RRNDm<"fcmp.d", 0x7E, I64, f64, simm7Op64, uimm6Op64>; +let cx = 1 in +defm FCPS : RRNDm<"fcmp.s", 0x7E, F32, f32, simm7Op32, uimm6Op32>; // Load and Store instructions // As 1st step, only uses sz and imm32 to represent $addr @@ -488,6 +628,55 @@ def EXTEND_STACK_GUARD : Pseudo<(outs), (ins), "# EXTEND STACK GUARD", []>; +// SETCC pattern matches +// +// CMP %tmp, lhs, rhs ; compare lhs and rhs +// or %res, 0, (0)1 ; initialize by 0 +// CMOV %res, (63)0, %tmp ; set 1 if %tmp is true + +def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrm0 (icond2cc $cond), + (CPXrr i64:$LHS, i64:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + +def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVLrm0 (icond2cc $cond), + (CMPrr i64:$LHS, i64:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + +def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrm0 (icond2cc $cond), + (CPSrr i32:$LHS, i32:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + +def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCUIOp:$cond)), + (EXTRACT_SUBREG + (CMOVWrm0 (icond2cc $cond), + (CMPUWrr i32:$LHS, i32:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + +def : Pat<(i32 (setcc f64:$LHS, f64:$RHS, cond:$cond)), + (EXTRACT_SUBREG + (CMOVDrm0 (fcond2cc $cond), + (FCPrr f64:$LHS, f64:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + +def : Pat<(i32 (setcc f32:$LHS, f32:$RHS, cond:$cond)), + (EXTRACT_SUBREG + (CMOVSrm0 (fcond2cc $cond), + (FCPSrr f32:$LHS, f32:$RHS), + 63, + (ORim1 0, 0)), sub_i32)>; + + // Several special pattern matches to optimize code def : Pat<(i32 (and i32:$lhs, 0xff)), diff --git a/llvm/test/CodeGen/VE/setccf32.ll b/llvm/test/CodeGen/VE/setccf32.ll new file mode 100644 index 000000000000..6ced8ce53b9c --- /dev/null +++ b/llvm/test/CodeGen/VE/setccf32.ll @@ -0,0 +1,187 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setccaf(float, float) { +; CHECK-LABEL: setccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp false float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccat(float, float) { +; CHECK-LABEL: setccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 1, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp true float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccoeq(float, float) { +; CHECK-LABEL: setccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oeq float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccone(float, float) { +; CHECK-LABEL: setccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp one float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccogt(float, float) { +; CHECK-LABEL: setccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccoge(float, float) { +; CHECK-LABEL: setccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccolt(float, float) { +; CHECK-LABEL: setccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccole(float, float) { +; CHECK-LABEL: setccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccord(float, float) { +; CHECK-LABEL: setccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ord float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuno(float, float) { +; CHECK-LABEL: setccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uno float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccueq(float, float) { +; CHECK-LABEL: setccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ueq float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccune(float, float) { +; CHECK-LABEL: setccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp une float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccugt(float, float) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuge(float, float) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccult(float, float) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult float %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccule(float, float) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule float %0, %1 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setccf32i.ll b/llvm/test/CodeGen/VE/setccf32i.ll new file mode 100644 index 000000000000..44bd6717545a --- /dev/null +++ b/llvm/test/CodeGen/VE/setccf32i.ll @@ -0,0 +1,211 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setccaf(float, float) { +; CHECK-LABEL: setccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp false float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccat(float, float) { +; CHECK-LABEL: setccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 1, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp true float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccoeq(float, float) { +; CHECK-LABEL: setccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oeq float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccone(float, float) { +; CHECK-LABEL: setccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp one float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccogt(float, float) { +; CHECK-LABEL: setccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccoge(float, float) { +; CHECK-LABEL: setccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccolt(float, float) { +; CHECK-LABEL: setccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccole(float, float) { +; CHECK-LABEL: setccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccord(float, float) { +; CHECK-LABEL: setccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s0 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.num %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ord float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccuno(float, float) { +; CHECK-LABEL: setccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.s %s1, %s0, %s0 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.nan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uno float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccueq(float, float) { +; CHECK-LABEL: setccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.eqnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ueq float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccune(float, float) { +; CHECK-LABEL: setccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.nenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp une float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccugt(float, float) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.gtnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccuge(float, float) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.genan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccult(float, float) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.ltnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult float %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccule(float, float) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: or %s1, 0, %s1 +; CHECK-NEXT: fcmp.s %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.s.lenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule float %0, 0.0 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setccf64.ll b/llvm/test/CodeGen/VE/setccf64.ll new file mode 100644 index 000000000000..dca40e8231fa --- /dev/null +++ b/llvm/test/CodeGen/VE/setccf64.ll @@ -0,0 +1,187 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setccaf(double, double) { +; CHECK-LABEL: setccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp false double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccat(double, double) { +; CHECK-LABEL: setccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 1, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp true double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccoeq(double, double) { +; CHECK-LABEL: setccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oeq double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccone(double, double) { +; CHECK-LABEL: setccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp one double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccogt(double, double) { +; CHECK-LABEL: setccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccoge(double, double) { +; CHECK-LABEL: setccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccolt(double, double) { +; CHECK-LABEL: setccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccole(double, double) { +; CHECK-LABEL: setccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccord(double, double) { +; CHECK-LABEL: setccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ord double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuno(double, double) { +; CHECK-LABEL: setccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uno double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccueq(double, double) { +; CHECK-LABEL: setccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ueq double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccune(double, double) { +; CHECK-LABEL: setccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp une double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccugt(double, double) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuge(double, double) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccult(double, double) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult double %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccule(double, double) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule double %0, %1 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setccf64i.ll b/llvm/test/CodeGen/VE/setccf64i.ll new file mode 100644 index 000000000000..59af1b4103f6 --- /dev/null +++ b/llvm/test/CodeGen/VE/setccf64i.ll @@ -0,0 +1,199 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setccaf(double, double) { +; CHECK-LABEL: setccaf: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp false double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccat(double, double) { +; CHECK-LABEL: setccat: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s0, 1, (0)1 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp true double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccoeq(double, double) { +; CHECK-LABEL: setccoeq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oeq double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccone(double, double) { +; CHECK-LABEL: setccone: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp one double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccogt(double, double) { +; CHECK-LABEL: setccogt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ogt double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccoge(double, double) { +; CHECK-LABEL: setccoge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp oge double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccolt(double, double) { +; CHECK-LABEL: setccolt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp olt double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccole(double, double) { +; CHECK-LABEL: setccole: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ole double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccord(double, double) { +; CHECK-LABEL: setccord: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s0 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.num %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ord double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccuno(double, double) { +; CHECK-LABEL: setccuno: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: fcmp.d %s1, %s0, %s0 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.nan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uno double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccueq(double, double) { +; CHECK-LABEL: setccueq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.eqnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ueq double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccune(double, double) { +; CHECK-LABEL: setccune: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.nenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp une double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccugt(double, double) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.gtnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ugt double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccuge(double, double) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.genan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp uge double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccult(double, double) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.ltnan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ult double %0, 0.0 + ret i1 %3 +} + +define zeroext i1 @setccule(double, double) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: lea.sl %s1, 0 +; CHECK-NEXT: fcmp.d %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.d.lenan %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = fcmp ule double %0, 0.0 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setcci32.ll b/llvm/test/CodeGen/VE/setcci32.ll new file mode 100644 index 000000000000..7e92a2c7f5ed --- /dev/null +++ b/llvm/test/CodeGen/VE/setcci32.ll @@ -0,0 +1,121 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setcceq(i32, i32) { +; CHECK-LABEL: setcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp eq i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccne(i32, i32) { +; CHECK-LABEL: setccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ne i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccugt(i32, i32) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuge(i32, i32) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccult(i32, i32) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccule(i32, i32) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsgt(i32, i32) { +; CHECK-LABEL: setccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsge(i32, i32) { +; CHECK-LABEL: setccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccslt(i32, i32) { +; CHECK-LABEL: setccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i32 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsle(i32, i32) { +; CHECK-LABEL: setccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i32 %0, %1 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setcci32i.ll b/llvm/test/CodeGen/VE/setcci32i.ll new file mode 100644 index 000000000000..c0d1fb0a67e4 --- /dev/null +++ b/llvm/test/CodeGen/VE/setcci32i.ll @@ -0,0 +1,131 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setcceq(i32, i32) { +; CHECK-LABEL: setcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp eq i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccne(i32, i32) { +; CHECK-LABEL: setccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ne i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccugt(i32, i32) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccuge(i32, i32) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccult(i32, i32) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccule(i32, i32) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.w %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsgt(i32, i32) { +; CHECK-LABEL: setccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsge(i32, i32) { +; CHECK-LABEL: setccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccslt(i32, i32) { +; CHECK-LABEL: setccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i32 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsle(i32, i32) { +; CHECK-LABEL: setccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.w.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i32 %0, 12 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setcci64.ll b/llvm/test/CodeGen/VE/setcci64.ll new file mode 100644 index 000000000000..8b86601594da --- /dev/null +++ b/llvm/test/CodeGen/VE/setcci64.ll @@ -0,0 +1,121 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setcceq(i64, i64) { +; CHECK-LABEL: setcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp eq i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccne(i64, i64) { +; CHECK-LABEL: setccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ne i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccugt(i64, i64) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccuge(i64, i64) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccult(i64, i64) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccule(i64, i64) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsgt(i64, i64) { +; CHECK-LABEL: setccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsge(i64, i64) { +; CHECK-LABEL: setccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.ge %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccslt(i64, i64) { +; CHECK-LABEL: setccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i64 %0, %1 + ret i1 %3 +} + +define zeroext i1 @setccsle(i64, i64) { +; CHECK-LABEL: setccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.le %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i64 %0, %1 + ret i1 %3 +} diff --git a/llvm/test/CodeGen/VE/setcci64i.ll b/llvm/test/CodeGen/VE/setcci64i.ll new file mode 100644 index 000000000000..aecbe40b0a34 --- /dev/null +++ b/llvm/test/CodeGen/VE/setcci64i.ll @@ -0,0 +1,131 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i1 @setcceq(i64, i64) { +; CHECK-LABEL: setcceq: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.eq %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp eq i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccne(i64, i64) { +; CHECK-LABEL: setccne: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.ne %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ne i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccugt(i64, i64) { +; CHECK-LABEL: setccugt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ugt i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccuge(i64, i64) { +; CHECK-LABEL: setccuge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp uge i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccult(i64, i64) { +; CHECK-LABEL: setccult: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ult i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccule(i64, i64) { +; CHECK-LABEL: setccule: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmpu.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp ule i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsgt(i64, i64) { +; CHECK-LABEL: setccsgt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sgt i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsge(i64, i64) { +; CHECK-LABEL: setccsge: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 11, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.gt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sge i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccslt(i64, i64) { +; CHECK-LABEL: setccslt: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 12, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp slt i64 %0, 12 + ret i1 %3 +} + +define zeroext i1 @setccsle(i64, i64) { +; CHECK-LABEL: setccsle: +; CHECK: .LBB{{[0-9]+}}_2: +; CHECK-NEXT: or %s1, 13, (0)1 +; CHECK-NEXT: cmps.l %s1, %s0, %s1 +; CHECK-NEXT: or %s0, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s0, (63)0, %s1 +; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0 +; CHECK-NEXT: or %s11, 0, %s9 + %3 = icmp sle i64 %0, 12 + ret i1 %3 +}