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[AArch64] Regenerate arm64-vector-ldst.ll test checks

This commit is contained in:
Simon Pilgrim 2022-07-16 15:27:41 +01:00
parent 2d4c43d45f
commit dc681bc2e0
1 changed files with 273 additions and 142 deletions
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415
llvm/test/CodeGen/AArch64/arm64-vector-ldst.ll
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@ -1,3 +1,4 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -verify-machineinstrs | FileCheck %s
; rdar://9428579
@ -8,10 +9,13 @@
define hidden fastcc void @t1(%type1** %argtable) nounwind {
entry:
; CHECK-LABEL: t1:
; CHECK: ldr x[[REG:[0-9]+]], [x0]
; CHECK: str q0, [x[[REG]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: str q0, [x8]
; CHECK-NEXT: ret
entry:
%tmp1 = load %type1*, %type1** %argtable, align 8
%tmp2 = getelementptr inbounds %type1, %type1* %tmp1, i64 0, i32 0
store <16 x i8> zeroinitializer, <16 x i8>* %tmp2, align 16
@ -19,10 +23,13 @@ entry:
}
define hidden fastcc void @t2(%type2** %argtable) nounwind {
entry:
; CHECK-LABEL: t2:
; CHECK: ldr x[[REG:[0-9]+]], [x0]
; CHECK: str d0, [x[[REG]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: movi.2d v0, #0000000000000000
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: str d0, [x8]
; CHECK-NEXT: ret
entry:
%tmp1 = load %type2*, %type2** %argtable, align 8
%tmp2 = getelementptr inbounds %type2, %type2* %tmp1, i64 0, i32 0
store <8 x i8> zeroinitializer, <8 x i8>* %tmp2, align 8
@ -45,12 +52,16 @@ entry:
@floatglobalArray32x2 = common global <2 x float>* null, align 8
define void @fct1_64x2(<2 x i64>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_64x2:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray64x2
; CHECK-NEXT: lsl x8, x1, #4
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray64x2]
; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 %offset
%tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
%tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
@ -60,11 +71,15 @@ entry:
}
define void @fct2_64x2(<2 x i64>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_64x2:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #80]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray64x2
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray64x2]
; CHECK-NEXT: ldr q0, [x0, #48]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str q0, [x8, #80]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <2 x i64>, <2 x i64>* %array, i64 3
%tmp = load <2 x i64>, <2 x i64>* %arrayidx, align 16
%tmp1 = load <2 x i64>*, <2 x i64>** @globalArray64x2, align 8
@ -74,12 +89,16 @@ entry:
}
define void @fct1_32x4(<4 x i32>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_32x4:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray32x4
; CHECK-NEXT: lsl x8, x1, #4
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray32x4]
; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 %offset
%tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
%tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
@ -89,11 +108,15 @@ entry:
}
define void @fct2_32x4(<4 x i32>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_32x4:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #80]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray32x4
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray32x4]
; CHECK-NEXT: ldr q0, [x0, #48]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str q0, [x8, #80]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <4 x i32>, <4 x i32>* %array, i64 3
%tmp = load <4 x i32>, <4 x i32>* %arrayidx, align 16
%tmp1 = load <4 x i32>*, <4 x i32>** @globalArray32x4, align 8
@ -103,12 +126,16 @@ entry:
}
define void @fct1_16x8(<8 x i16>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_16x8:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray16x8
; CHECK-NEXT: lsl x8, x1, #4
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray16x8]
; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 %offset
%tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
%tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
@ -118,11 +145,15 @@ entry:
}
define void @fct2_16x8(<8 x i16>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_16x8:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #80]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray16x8
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray16x8]
; CHECK-NEXT: ldr q0, [x0, #48]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str q0, [x8, #80]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <8 x i16>, <8 x i16>* %array, i64 3
%tmp = load <8 x i16>, <8 x i16>* %arrayidx, align 16
%tmp1 = load <8 x i16>*, <8 x i16>** @globalArray16x8, align 8
@ -132,12 +163,16 @@ entry:
}
define void @fct1_8x16(<16 x i8>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_8x16:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #4
; CHECK: ldr [[DEST:q[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray8x16
; CHECK-NEXT: lsl x8, x1, #4
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray8x16]
; CHECK-NEXT: ldr q0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str q0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 %offset
%tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
%tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
@ -147,11 +182,15 @@ entry:
}
define void @fct2_8x16(<16 x i8>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_8x16:
; CHECK: ldr [[DEST:q[0-9]+]], [x0, #48]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #80]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray8x16
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray8x16]
; CHECK-NEXT: ldr q0, [x0, #48]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str q0, [x8, #80]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <16 x i8>, <16 x i8>* %array, i64 3
%tmp = load <16 x i8>, <16 x i8>* %arrayidx, align 16
%tmp1 = load <16 x i8>*, <16 x i8>** @globalArray8x16, align 8
@ -161,12 +200,16 @@ entry:
}
define void @fct1_64x1(<1 x i64>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_64x1:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray64x1
; CHECK-NEXT: lsl x8, x1, #3
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray64x1]
; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str d0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 %offset
%tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
%tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
@ -176,11 +219,15 @@ entry:
}
define void @fct2_64x1(<1 x i64>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_64x1:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #40]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray64x1
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray64x1]
; CHECK-NEXT: ldr d0, [x0, #24]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str d0, [x8, #40]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <1 x i64>, <1 x i64>* %array, i64 3
%tmp = load <1 x i64>, <1 x i64>* %arrayidx, align 8
%tmp1 = load <1 x i64>*, <1 x i64>** @globalArray64x1, align 8
@ -190,12 +237,16 @@ entry:
}
define void @fct1_32x2(<2 x i32>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_32x2:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray32x2
; CHECK-NEXT: lsl x8, x1, #3
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray32x2]
; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str d0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 %offset
%tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
%tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
@ -205,11 +256,15 @@ entry:
}
define void @fct2_32x2(<2 x i32>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_32x2:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #40]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray32x2
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray32x2]
; CHECK-NEXT: ldr d0, [x0, #24]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str d0, [x8, #40]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <2 x i32>, <2 x i32>* %array, i64 3
%tmp = load <2 x i32>, <2 x i32>* %arrayidx, align 8
%tmp1 = load <2 x i32>*, <2 x i32>** @globalArray32x2, align 8
@ -219,12 +274,16 @@ entry:
}
define void @fct1_16x4(<4 x i16>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_16x4:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray16x4
; CHECK-NEXT: lsl x8, x1, #3
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray16x4]
; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str d0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 %offset
%tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
%tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
@ -234,11 +293,15 @@ entry:
}
define void @fct2_16x4(<4 x i16>* nocapture %array) nounwind ssp {
entry:
; CHECK-LABEL: fct2_16x4:
; CHECK: ldr [[DEST:d[0-9]+]], [x0, #24]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], #40]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x8, :got:globalArray16x4
; CHECK-NEXT: ldr x8, [x8, :got_lo12:globalArray16x4]
; CHECK-NEXT: ldr d0, [x0, #24]
; CHECK-NEXT: ldr x8, [x8]
; CHECK-NEXT: str d0, [x8, #40]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <4 x i16>, <4 x i16>* %array, i64 3
%tmp = load <4 x i16>, <4 x i16>* %arrayidx, align 8
%tmp1 = load <4 x i16>*, <4 x i16>** @globalArray16x4, align 8
@ -248,12 +311,16 @@ entry:
}
define void @fct1_8x8(<8 x i8>* nocapture %array, i64 %offset) nounwind ssp {
entry:
; CHECK-LABEL: fct1_8x8:
; CHECK: lsl [[SHIFTEDOFFSET:x[0-9]+]], x1, #3
; CHECK: ldr [[DEST:d[0-9]+]], [x0, [[SHIFTEDOFFSET]]]
; CHECK: ldr [[BASE:x[0-9]+]],
; CHECK: str [[DEST]], [[[BASE]], [[SHIFTEDOFFSET]]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: adrp x9, :got:globalArray8x8
; CHECK-NEXT: lsl x8, x1, #3
; CHECK-NEXT: ldr x9, [x9, :got_lo12:globalArray8x8]
; CHECK-NEXT: ldr d0, [x0, x8]
; CHECK-NEXT: ldr x9, [x9]
; CHECK-NEXT: str d0, [x9, x8]
; CHECK-NEXT: ret
entry:
%arrayidx = getelementptr inbounds <8 x i8>, <8 x i8>* %array, i64 %offset
%tmp = load <8 x i8>, <8 x i8>* %arrayidx, align 8
%tmp1 = load <8 x i8>*, <8 x i8>** @globalArray8x8, align 8
@ -266,9 +333,11 @@ entry:
; registers for unscaled vector accesses
define <1 x i64> @fct0(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct0:
; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <1 x i64>*
%0 = load <1 x i64>, <1 x i64>* %q, align 8
@ -276,9 +345,11 @@ entry:
}
define <2 x i32> @fct1(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct1:
; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i32>*
%0 = load <2 x i32>, <2 x i32>* %q, align 8
@ -286,9 +357,11 @@ entry:
}
define <4 x i16> @fct2(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct2:
; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i16>*
%0 = load <4 x i16>, <4 x i16>* %q, align 8
@ -296,9 +369,11 @@ entry:
}
define <8 x i8> @fct3(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct3:
; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i8>*
%0 = load <8 x i8>, <8 x i8>* %q, align 8
@ -306,9 +381,11 @@ entry:
}
define <2 x i64> @fct4(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct4:
; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i64>*
%0 = load <2 x i64>, <2 x i64>* %q, align 16
@ -316,9 +393,11 @@ entry:
}
define <4 x i32> @fct5(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct5:
; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i32>*
%0 = load <4 x i32>, <4 x i32>* %q, align 16
@ -326,9 +405,11 @@ entry:
}
define <8 x i16> @fct6(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct6:
; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i16>*
%0 = load <8 x i16>, <8 x i16>* %q, align 16
@ -336,9 +417,11 @@ entry:
}
define <16 x i8> @fct7(i8* %str) nounwind readonly ssp {
entry:
; CHECK-LABEL: fct7:
; CHECK: ldur {{q[0-9]+}}, [{{x[0-9]+}}, #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <16 x i8>*
%0 = load <16 x i8>, <16 x i8>* %q, align 16
@ -346,10 +429,12 @@ entry:
}
define void @fct8(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct8:
; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: stur d0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <1 x i64>*
%0 = load <1 x i64>, <1 x i64>* %q, align 8
@ -360,10 +445,12 @@ entry:
}
define void @fct9(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct9:
; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: stur d0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i32>*
%0 = load <2 x i32>, <2 x i32>* %q, align 8
@ -374,10 +461,12 @@ entry:
}
define void @fct10(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct10:
; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: stur d0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i16>*
%0 = load <4 x i16>, <4 x i16>* %q, align 8
@ -388,10 +477,12 @@ entry:
}
define void @fct11(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct11:
; CHECK: ldur [[DESTREG:d[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur d0, [x0, #3]
; CHECK-NEXT: stur d0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i8>*
%0 = load <8 x i8>, <8 x i8>* %q, align 8
@ -402,10 +493,12 @@ entry:
}
define void @fct12(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct12:
; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: stur q0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <2 x i64>*
%0 = load <2 x i64>, <2 x i64>* %q, align 16
@ -416,10 +509,12 @@ entry:
}
define void @fct13(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct13:
; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: stur q0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <4 x i32>*
%0 = load <4 x i32>, <4 x i32>* %q, align 16
@ -430,10 +525,12 @@ entry:
}
define void @fct14(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct14:
; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: stur q0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <8 x i16>*
%0 = load <8 x i16>, <8 x i16>* %q, align 16
@ -444,10 +541,12 @@ entry:
}
define void @fct15(i8* %str) nounwind ssp {
entry:
; CHECK-LABEL: fct15:
; CHECK: ldur [[DESTREG:q[0-9]+]], [[[BASEREG:x[0-9]+]], #3]
; CHECK: stur [[DESTREG]], [[[BASEREG]], #4]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldur q0, [x0, #3]
; CHECK-NEXT: stur q0, [x0, #4]
; CHECK-NEXT: ret
entry:
%p = getelementptr inbounds i8, i8* %str, i64 3
%q = bitcast i8* %p to <16 x i8>*
%0 = load <16 x i8>, <16 x i8>* %q, align 16
@ -463,8 +562,10 @@ entry:
; Single loads with immediate offset.
define <8 x i8> @fct16(i8* nocapture %sp0) {
; CHECK-LABEL: fct16:
; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #1]
; CHECK-NEXT: mul.8b v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@ -475,8 +576,10 @@ entry:
define <16 x i8> @fct17(i8* nocapture %sp0) {
; CHECK-LABEL: fct17:
; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, #1]
; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, #1]
; CHECK-NEXT: mul.16b v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 1
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@ -487,8 +590,10 @@ entry:
define <4 x i16> @fct18(i16* nocapture %sp0) {
; CHECK-LABEL: fct18:
; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0, #2]
; CHECK-NEXT: mul.4h v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@ -499,8 +604,10 @@ entry:
define <8 x i16> @fct19(i16* nocapture %sp0) {
; CHECK-LABEL: fct19:
; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, #2]
; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0, #2]
; CHECK-NEXT: mul.8h v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 1
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@ -511,8 +618,10 @@ entry:
define <2 x i32> @fct20(i32* nocapture %sp0) {
; CHECK-LABEL: fct20:
; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0, #4]
; CHECK-NEXT: mul.2s v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@ -523,8 +632,10 @@ entry:
define <4 x i32> @fct21(i32* nocapture %sp0) {
; CHECK-LABEL: fct21:
; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, #4]
; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0, #4]
; CHECK-NEXT: mul.4s v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 1
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@ -535,7 +646,9 @@ entry:
define <1 x i64> @fct22(i64* nocapture %sp0) {
; CHECK-LABEL: fct22:
; CHECK: ldr d0, [x0, #8]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d0, [x0, #8]
; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@ -545,7 +658,9 @@ entry:
define <2 x i64> @fct23(i64* nocapture %sp0) {
; CHECK-LABEL: fct23:
; CHECK: ldr d[[REGNUM:[0-9]+]], [x0, #8]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d0, [x0, #8]
; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 1
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@ -557,8 +672,10 @@ entry:
; Single loads with register offset.
define <8 x i8> @fct24(i8* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct24:
; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
; CHECK-NEXT: mul.8b v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, x1]
; CHECK-NEXT: mul.8b v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@ -569,8 +686,10 @@ entry:
define <16 x i8> @fct25(i8* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct25:
; CHECK: ldr b[[REGNUM:[0-9]+]], [x0, x1]
; CHECK-NEXT: mul.16b v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr b0, [x0, x1]
; CHECK-NEXT: mul.16b v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i8, i8* %sp0, i64 %offset
%pix_sp0.0.copyload = load i8, i8* %addr, align 1
@ -581,8 +700,10 @@ entry:
define <4 x i16> @fct26(i16* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct26:
; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
; CHECK-NEXT: mul.4h v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
; CHECK-NEXT: mul.4h v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@ -593,8 +714,10 @@ entry:
define <8 x i16> @fct27(i16* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct27:
; CHECK: ldr h[[REGNUM:[0-9]+]], [x0, x1, lsl #1]
; CHECK-NEXT: mul.8h v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr h0, [x0, x1, lsl #1]
; CHECK-NEXT: mul.8h v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i16, i16* %sp0, i64 %offset
%pix_sp0.0.copyload = load i16, i16* %addr, align 1
@ -605,8 +728,10 @@ entry:
define <2 x i32> @fct28(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct28:
; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
; CHECK-NEXT: mul.2s v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
; CHECK-NEXT: mul.2s v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@ -617,8 +742,10 @@ entry:
define <4 x i32> @fct29(i32* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct29:
; CHECK: ldr s[[REGNUM:[0-9]+]], [x0, x1, lsl #2]
; CHECK-NEXT: mul.4s v0, v[[REGNUM]], v[[REGNUM]]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr s0, [x0, x1, lsl #2]
; CHECK-NEXT: mul.4s v0, v0, v0
; CHECK-NEXT: ret
entry:
%addr = getelementptr i32, i32* %sp0, i64 %offset
%pix_sp0.0.copyload = load i32, i32* %addr, align 1
@ -629,7 +756,9 @@ entry:
define <1 x i64> @fct30(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct30:
; CHECK: ldr d0, [x0, x1, lsl #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]
; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1
@ -639,7 +768,9 @@ entry:
define <2 x i64> @fct31(i64* nocapture %sp0, i64 %offset) {
; CHECK-LABEL: fct31:
; CHECK: ldr d0, [x0, x1, lsl #3]
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldr d0, [x0, x1, lsl #3]
; CHECK-NEXT: ret
entry:
%addr = getelementptr i64, i64* %sp0, i64 %offset
%pix_sp0.0.copyload = load i64, i64* %addr, align 1