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ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. 

llvm-svn: 63509
This commit is contained in:
Evan Cheng 2009-02-02 09:15:04 +00:00
parent 7e4cb0a1cf
commit dc636c4080
1 changed files with 8 additions and 0 deletions
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8
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -7515,6 +7515,14 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything.
switch (Opc) { switch (Opc) {
default: break; default: break;
case X86ISD::ADD:
case X86ISD::SUB:
case X86ISD::SMUL:
case X86ISD::UMUL:
// These nodes' second result is a boolean.
if (Op.getResNo() == 0)
break;
// Fallthrough
case X86ISD::SETCC: case X86ISD::SETCC:
KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
Mask.getBitWidth() - 1); Mask.getBitWidth() - 1);