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[X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode. 

llvm-svn: 333717
This commit is contained in:
Craig Topper 2018-06-01 01:23:52 +00:00
parent 1eb074d76e
commit dc5ba1e495
2 changed files with 7 additions and 1 deletions
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4
llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
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@ -1695,7 +1695,7 @@ static int readVVVV(struct InternalInstruction* insn) {
return -1; return -1;
if (insn->mode != MODE_64BIT) if (insn->mode != MODE_64BIT)
vvvv &= 0x7; vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
insn->vvvv = static_cast<Reg>(vvvv); insn->vvvv = static_cast<Reg>(vvvv);
return 0; return 0;
@ -1860,6 +1860,8 @@ static int readOperands(struct InternalInstruction* insn) {
needVVVV = 0; /* Mark that we have found a VVVV operand. */ needVVVV = 0; /* Mark that we have found a VVVV operand. */
if (!hasVVVV) if (!hasVVVV)
return -1; return -1;
if (insn->mode != MODE_64BIT)
insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
if (fixupReg(insn, &Op)) if (fixupReg(insn, &Op))
return -1; return -1;
break; break;

4
llvm/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt Normal file
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@ -0,0 +1,4 @@
# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 2>&1 | grep "invalid instruction encoding"
# Make sure the VEX.vvvv being all 1s check doesn't ignore bit 3 in 32-bit mode.
0xc4 0xe1 0xb9 0x7e 0xc0