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Update ARM STM tests. Fix check: prefix for diagnostic tests. 

llvm-svn: 136088
This commit is contained in:
Jim Grosbach 2011-07-26 15:41:22 +00:00
parent fe44f67d43
commit dc45f00cf5
2 changed files with 88 additions and 79 deletions
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39
llvm/test/MC/ARM/basic-arm-instructions.s
View File

@ -1669,25 +1669,26 @@ _func:
@ STM*
@------------------------------------------------------------------------------
stm r2, {r1,r3-r6,sp}
stmia r2, {r1,r3-r6,sp}
stmib r2, {r1,r3-r6,sp}
stmda r2, {r1,r3-r6,sp}
stmdb r2, {r1,r3-r6,sp}
stmfd r2, {r1,r3-r6,sp}
stmia r3, {r1,r3-r6,lr}
stmib r4, {r1,r3-r6,sp}
stmda r5, {r1,r3-r6,sp}
stmdb r6, {r1,r3-r6,r8}
stmfd sp, {r1,r3-r6,sp}
@ with update
stmia r2!, {r1,r3-r6,sp}
stmib r2!, {r1,r3-r6,sp}
stmda r2!, {r1,r3-r6,sp}
stmdb r2!, {r1,r3-r6,sp}
@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
@ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9]
@ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8]
@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9]
stm r8!, {r1,r3-r6,sp}
stmib r9!, {r1,r3-r6,sp}
stmda sp!, {r1,r3-r6}
stmdb r0!, {r1,r5,r7,sp}
@ CHECK: stm r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe8]
@ CHECK: stmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa2,0xe9]
@ CHECK: stmda r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe8]
@ CHECK: stmdb r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x22,0xe9]
@ CHECK: stm r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8]
@ CHECK: stm r3, {lr, r1, r3, r4, r5, r6} @ encoding: [0x7a,0x40,0x83,0xe8]
@ CHECK: stmib r4, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x84,0xe9]
@ CHECK: stmda r5, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x05,0xe8]
@ CHECK: stmdb r6, {r1, r3, r4, r5, r6, r8} @ encoding: [0x7a,0x01,0x06,0xe9]
@ CHECK: stmdb sp, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x0d,0xe9]
@ CHECK: stm r8!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa8,0xe8]
@ CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xa9,0xe9]
@ CHECK: stmda sp!, {r1, r3, r4, r5, r6} @ encoding: [0x7a,0x00,0x2d,0xe8]
@ CHECK: stmdb r0!, {r1, r5, r7, sp} @ encoding: [0xa2,0x20,0x20,0xe9]

128
llvm/test/MC/ARM/diagnostics.s
View File

@ -126,24 +126,24 @@
pkhbt r2, r2, r3, asr #3
pkhtb r2, r2, r3, lsl #3
@ CHECK: error: immediate value out of range
@ CHECK: pkhbt r2, r2, r3, lsl #-1
@ CHECK: ^
@ CHECK: error: immediate value out of range
@ CHECK: pkhbt r2, r2, r3, lsl #32
@ CHECK: ^
@ CHECK: error: immediate value out of range
@ CHECK: pkhtb r2, r2, r3, asr #0
@ CHECK: ^
@ CHECK: error: immediate value out of range
@ CHECK: pkhtb r2, r2, r3, asr #33
@ CHECK: ^
@ CHECK: error: lsl operand expected.
@ CHECK: pkhbt r2, r2, r3, asr #3
@ CHECK: ^
@ CHECK: error: asr operand expected.
@ CHECK: pkhtb r2, r2, r3, lsl #3
@ CHECK: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhbt r2, r2, r3, lsl #32
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #0
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: immediate value out of range
@ CHECK-ERRORS: pkhtb r2, r2, r3, asr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: lsl operand expected.
@ CHECK-ERRORS: pkhbt r2, r2, r3, asr #3
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: asr operand expected.
@ CHECK-ERRORS: pkhtb r2, r2, r3, lsl #3
@ CHECK-ERRORS: ^
@ bad values for SETEND
@ -151,15 +151,15 @@
setend me
setend 1
@ CHECK: error: instruction 'setend' is not predicable, but condition code specified
@ CHECK: setendne be
@ CHECK: ^
@ CHECK: error: 'be' or 'le' operand expected
@ CHECK: setend me
@ CHECK: ^
@ CHECK: error: 'be' or 'le' operand expected
@ CHECK: setend 1
@ CHECK: ^
@ CHECK-ERRORS: error: instruction 'setend' is not predicable, but condition code specified
@ CHECK-ERRORS: setendne be
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'be' or 'le' operand expected
@ CHECK-ERRORS: setend me
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'be' or 'le' operand expected
@ CHECK-ERRORS: setend 1
@ CHECK-ERRORS: ^
@ Out of range immediates and bad shift types for SSAT
@ -173,41 +173,49 @@
ssat r8, #1, r10, lsl fred
ssat r8, #1, r10, lsl #fred
@ CHECK: error: invalid operand for instruction
@ CHECK: ssat r8, #0, r10, lsl #8
@ CHECK: ^
@ CHECK: error: invalid operand for instruction
@ CHECK: ssat r8, #33, r10, lsl #8
@ CHECK: ^
@ CHECK: error: 'lsr' shift amount must be in range [0,31]
@ CHECK: ssat r8, #1, r10, lsl #-1
@ CHECK: ^
@ CHECK: error: 'lsr' shift amount must be in range [0,31]
@ CHECK: ssat r8, #1, r10, lsl #32
@ CHECK: ^
@ CHECK: error: 'asr' shift amount must be in range [1,32]
@ CHECK: ssat r8, #1, r10, asr #0
@ CHECK: ^
@ CHECK: error: 'asr' shift amount must be in range [1,32]
@ CHECK: ssat r8, #1, r10, asr #33
@ CHECK: ^
@ CHECK: error: shift operator 'asr' or 'lsl' expected
@ CHECK: ssat r8, #1, r10, lsr #5
@ CHECK: ^
@ CHECK: error: '#' expected
@ CHECK: ssat r8, #1, r10, lsl fred
@ CHECK: ^
@ CHECK: error: shift amount must be an immediate
@ CHECK: ssat r8, #1, r10, lsl #fred
@ CHECK: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat r8, #0, r10, lsl #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat r8, #33, r10, lsl #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #-1
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'lsr' shift amount must be in range [0,31]
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #32
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
@ CHECK-ERRORS: ssat r8, #1, r10, asr #0
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: 'asr' shift amount must be in range [1,32]
@ CHECK-ERRORS: ssat r8, #1, r10, asr #33
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: shift operator 'asr' or 'lsl' expected
@ CHECK-ERRORS: ssat r8, #1, r10, lsr #5
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: '#' expected
@ CHECK-ERRORS: ssat r8, #1, r10, lsl fred
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: shift amount must be an immediate
@ CHECK-ERRORS: ssat r8, #1, r10, lsl #fred
@ CHECK-ERRORS: ^
@ Out of range immediates for SSAT16
ssat16 r2, #0, r7
ssat16 r3, #17, r5
@ CHECK: error: invalid operand for instruction
@ CHECK: ssat16 r2, #0, r7
@ CHECK: ^
@ CHECK: error: invalid operand for instruction
@ CHECK: ssat16 r3, #17, r5
@ CHECK: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat16 r2, #0, r7
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: ssat16 r3, #17, r5
@ CHECK-ERRORS: ^
@ Out of order STM registers
stmda sp!, {r5, r2}
@ CHECK-ERRORS: warning: register not in ascending order in register list
@ CHECK-ERRORS: stmda sp!, {r5, r2}
@ CHECK-ERRORS: ^