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Remove unsafe AssertZext after promoting result of FP_TO_FP16 

Summary:
Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32
instruction, do not guarantee that the top 16 bits are zeroed out.
Remove the unsafe AssertZext and add tests to exercise this.

Reviewers: jmolloy, sbaranga, kristof.beyls, aadg

Subscribers: llvm-commits, srhines, aemerson

Differential Revision: http://reviews.llvm.org/D18426

llvm-svn: 264285
This commit is contained in:
Pirama Arumuga Nainar 2016-03-24 14:06:03 +00:00
parent 733ea34f38
commit dc45aef2d8
2 changed files with 13 additions and 4 deletions
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5
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -436,10 +436,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_FP16(SDNode *N) {
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
SDLoc dl(N);
SDValue Res = DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
return DAG.getNode(ISD::AssertZext, dl,
NVT, Res, DAG.getValueType(N->getValueType(0)));
return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {

12
llvm/test/CodeGen/ARM/fp16-v3.ll
View File

@ -25,4 +25,16 @@ define void @test_vec3(<3 x half>* %arr, i32 %i) #0 {
ret void
}
; CHECK-LABEL: test_bitcast:
; CHECK: vcvtb.f16.f32
; CHECK: vcvtb.f16.f32
; CHECK: vcvtb.f16.f32
; CHECK: pkhbt
; CHECK: uxth
define void @test_bitcast(<3 x half> %inp, <3 x i16>* %arr) #0 {
%bc = bitcast <3 x half> %inp to <3 x i16>
store <3 x i16> %bc, <3 x i16>* %arr, align 8
ret void
}
attributes #0 = { nounwind }