maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Remove the predicates from the register forms of the 2-byte inc and dec instructions. Remove the 32-bit mode only versions that existed for the disassembler. Move the patterns out of the instructions so they can still be qualified with predicates. 

llvm-svn: 225157
This commit is contained in:
Craig Topper 2015-01-05 08:19:12 +00:00
parent 3dcdde2e92
commit dc2fc8035d
2 changed files with 24 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
llvm/lib/Target/X86/X86InstrArithmetic.td
View File

@ -459,13 +459,10 @@ def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
"inc{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
"inc{w}\t$dst", [], IIC_UNARY_REG>,
OpSize16, Requires<[Not64BitMode]>;
def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
"inc{l}\t$dst",
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
IIC_UNARY_REG>,
"inc{l}\t$dst", [], IIC_UNARY_REG>,
OpSize32, Requires<[Not64BitMode]>;
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
@ -477,43 +474,15 @@ def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
let isConvertibleToThreeAddress = 1, CodeSize = 2 in {
// Can transform into LEA.
def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
"inc{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
IIC_UNARY_REG>,
OpSize16, Requires<[In64BitMode]>;
"inc{w}\t$dst", [], IIC_UNARY_REG>, OpSize16;
def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
"inc{l}\t$dst",
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
IIC_UNARY_REG>,
OpSize32, Requires<[In64BitMode]>;
"inc{l}\t$dst", [], IIC_UNARY_REG>, OpSize32;
def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
"dec{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
IIC_UNARY_REG>,
OpSize16, Requires<[In64BitMode]>;
"dec{w}\t$dst", [], IIC_UNARY_REG>, OpSize16;
def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
"dec{l}\t$dst",
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
IIC_UNARY_REG>,
OpSize32, Requires<[In64BitMode]>;
"dec{l}\t$dst", [], IIC_UNARY_REG>, OpSize32;
} // isConvertibleToThreeAddress = 1, CodeSize = 2
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
CodeSize = 2 in {
def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
"inc{w}\t$dst", [], IIC_UNARY_REG>,
OpSize16, Requires<[Not64BitMode]>;
def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
"inc{l}\t$dst", [], IIC_UNARY_REG>,
OpSize32, Requires<[Not64BitMode]>;
def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
"dec{w}\t$dst", [], IIC_UNARY_REG>,
OpSize16, Requires<[Not64BitMode]>;
def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
"dec{l}\t$dst", [], IIC_UNARY_REG>,
OpSize32, Requires<[Not64BitMode]>;
} // isCodeGenOnly = 1, ForceDisassemble = 1, HasSideEffects = 0, CodeSize = 2
} // Constraints = "$src1 = $dst", SchedRW
let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
@ -561,14 +530,10 @@ def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
IIC_UNARY_REG>;
let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
"dec{w}\t$dst",
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
IIC_UNARY_REG>,
"dec{w}\t$dst", [], IIC_UNARY_REG>,
OpSize16, Requires<[Not64BitMode]>;
def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
"dec{l}\t$dst",
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
IIC_UNARY_REG>,
"dec{l}\t$dst", [], IIC_UNARY_REG>,
OpSize32, Requires<[Not64BitMode]>;
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
@ -595,6 +560,20 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
} // CodeSize = 2, SchedRW
} // Defs = [EFLAGS]
let Predicates = [Not64BitMode] in {
def : Pat<(X86inc_flag GR16:$src1), (INC16r GR16:$src1)>;
def : Pat<(X86inc_flag GR32:$src1), (INC32r GR32:$src1)>;
def : Pat<(X86dec_flag GR16:$src1), (DEC16r GR16:$src1)>;
def : Pat<(X86dec_flag GR32:$src1), (DEC32r GR32:$src1)>;
}
let Predicates = [In64BitMode] in {
def : Pat<(X86inc_flag GR16:$src1), (INC64_16r GR16:$src1)>;
def : Pat<(X86inc_flag GR32:$src1), (INC64_32r GR32:$src1)>;
def : Pat<(X86dec_flag GR16:$src1), (DEC64_16r GR16:$src1)>;
def : Pat<(X86dec_flag GR32:$src1), (DEC64_32r GR32:$src1)>;
}
/// X86TypeInfo - This is a bunch of information that describes relevant X86
/// information about value types. For example, it can tell you what the
/// register class and preferred load to use.

3
llvm/lib/Target/X86/X86InstrInfo.td
View File

@ -32,7 +32,8 @@ def SDTX86Cmov : SDTypeProfile<1, 4,
// Unary and binary operator instructions that set EFLAGS as a side-effect.
def SDTUnaryArithWithFlags : SDTypeProfile<2, 1,
[SDTCisInt<0>, SDTCisVT<1, i32>]>;
[SDTCisSameAs<0, 2>,
SDTCisInt<0>, SDTCisVT<1, i32>]>;
def SDTBinaryArithWithFlags : SDTypeProfile<2, 2,
[SDTCisSameAs<0, 2>,