forked from OSchip/llvm-project
The purpose of the patch is to fix the syntax of ARM mrc and mrc2 instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility.
llvm-svn: 181705
This commit is contained in:
Mihai Popa
parent
27699c8e5b
commit
dc1764c5a4
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@ -94,6 +94,7 @@ getReservedRegs(const MachineFunction &MF) const {
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Reserved.set(ARM::SP);
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Reserved.set(ARM::PC);
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Reserved.set(ARM::FPSCR);
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Reserved.set(ARM::APSR_NZCV);
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if (TFI->hasFP(MF))
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Reserved.set(FramePtr);
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if (hasBasePointer(MF))
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@ -4636,11 +4636,11 @@ def : ARMInstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0, pred:$p)>;
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def MRC : MovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt),
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(outs GPRwithAPSR:$Rt),
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(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
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imm0_7:$opc2), []>;
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def : ARMInstAlias<"mrc${p} $cop, $opc1, $Rt, $CRn, $CRm",
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(MRC GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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(MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0, pred:$p)>;
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def : ARMPat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
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@ -4650,7 +4650,7 @@ class MovRCopro2<string opc, bit direction, dag oops, dag iops,
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list<dag> pattern>
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: ABXI<0b1110, oops, iops, NoItinerary,
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!strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), pattern> {
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let Inst{31-28} = 0b1111;
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let Inst{31-24} = 0b11111110;
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let Inst{20} = direction;
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let Inst{4} = 1;
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@ -4679,11 +4679,11 @@ def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
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(MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
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(outs GPR:$Rt),
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(outs GPRwithAPSR:$Rt),
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(ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
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imm0_7:$opc2), []>;
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def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
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(MRC2 GPR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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(MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
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c_imm:$CRm, 0)>;
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def : ARMV5TPat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn,
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@ -157,12 +157,15 @@ def Q15 : ARMReg<15, "q15", [D30, D31]>;
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// Current Program Status Register.
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// We model fpscr with two registers: FPSCR models the control bits and will be
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// reserved. FPSCR_NZCV models the flag bits and will be unreserved.
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def CPSR : ARMReg<0, "cpsr">;
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def APSR : ARMReg<1, "apsr">;
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def SPSR : ARMReg<2, "spsr">;
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def FPSCR : ARMReg<3, "fpscr">;
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def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {
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// reserved. FPSCR_NZCV models the flag bits and will be unreserved. APSR_NZCV
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// models the APSR when it's accessed by some special instructions. In such cases
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// it has the same encoding as PC.
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def CPSR : ARMReg<0, "cpsr">;
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def APSR : ARMReg<1, "apsr">;
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def APSR_NZCV : ARMReg<15, "apsr_nzcv">;
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def SPSR : ARMReg<2, "spsr">;
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def FPSCR : ARMReg<3, "fpscr">;
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def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {
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let Aliases = [FPSCR];
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}
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def ITSTATE : ARMReg<4, "itstate">;
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@ -207,6 +210,16 @@ def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
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}];
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}
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// GPRs without the PC but with APSR. Some instructions allow accessing the
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// APSR, while actually encoding PC in the register field. This is usefull
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// for assembly and disassembly only.
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def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add GPR, APSR_NZCV)> {
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let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
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let AltOrderSelect = [{
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return 1 + MF.getTarget().getSubtarget<ARMSubtarget>().isThumb1Only();
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}];
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}
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// GPRsp - Only the SP is legal. Used by Thumb1 instructions that want the
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// implied SP argument list.
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// FIXME: It would be better to not use this at all and refactor the
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@ -156,6 +156,9 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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@ -920,6 +923,21 @@ DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
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return S;
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}
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static DecodeStatus
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DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = MCDisassembler::Success;
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if (RegNo == 15)
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{
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Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
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return MCDisassembler::Success;
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}
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Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
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return S;
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}
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static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 7)
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@ -1062,10 +1062,18 @@ Lforward:
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@ MRC/MRC2
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@------------------------------------------------------------------------------
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mrc p14, #0, r1, c1, c2, #4
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mrc p15, #7, apsr_nzcv, c15, c6, #6
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mrc p15, #7, pc, c15, c6, #6
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mrc2 p14, #0, r1, c1, c2, #4
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mrc2 p10, #7, apsr_nzcv, c15, c0, #1
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mrc2 p10, #7, pc, c15, c0, #1
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@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
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@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
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@ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xee]
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@ CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
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@ CHECK: mrc p15, #7, pc, c15, c6, #6 @ encoding: [0xd6,0xff,0xff,0xee]
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@ CHECK: mrc2 p14, #0, r1, c1, c2, #4 @ encoding: [0x92,0x1e,0x11,0xfe]
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@ CHECK: mrc2 p10, #7, apsr_nzcv, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
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@ CHECK: mrc2 p10, #7, pc, c15, c0, #1 @ encoding: [0x30,0xfa,0xff,0xfe]
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@------------------------------------------------------------------------------
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@ MRRC/MRRC2
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@ -757,10 +757,14 @@
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# MRC/MRC2
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#------------------------------------------------------------------------------
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# CHECK: mrc p14, #0, r1, c1, c2, #4
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# CHECK: mrc p15, #7, apsr_nzcv, c15, c6, #6
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# CHECK: mrc2 p14, #0, r1, c1, c2, #4
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# CHECK: mrc2 p9, #7, apsr_nzcv, c15, c0, #1
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0x92 0x1e 0x11 0xee
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0xd6 0xff 0xff 0xee
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0x92 0x1e 0x11 0xfe
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0x30 0xf9 0xff 0xfe
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#------------------------------------------------------------------------------
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# MRRC/MRRC2
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