forked from OSchip/llvm-project
[NFC][ARM] Add test
This commit is contained in:
Sam Parker
parent
17fadeffcc
commit
dc0d84f09e
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@ -0,0 +1,533 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - | FileCheck %s
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--- |
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define dso_local arm_aapcs_vfpcc void @unrolled_and_vector(i8* nocapture %res, i8* nocapture readonly %a, i8* nocapture readonly %b, i32 %N) {
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entry:
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%cmp10 = icmp eq i32 %N, 0
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br i1 %cmp10, label %for.cond.cleanup, label %vector.memcheck
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vector.memcheck: ; preds = %entry
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%scevgep = getelementptr i8, i8* %res, i32 %N
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%scevgep12 = getelementptr i8, i8* %a, i32 %N
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%scevgep13 = getelementptr i8, i8* %b, i32 %N
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%bound0 = icmp ugt i8* %scevgep12, %res
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%bound1 = icmp ugt i8* %scevgep, %a
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%found.conflict = and i1 %bound0, %bound1
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%bound014 = icmp ugt i8* %scevgep13, %res
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%bound115 = icmp ugt i8* %scevgep, %b
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%found.conflict16 = and i1 %bound014, %bound115
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%conflict.rdx = or i1 %found.conflict, %found.conflict16
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%0 = add i32 %N, 15
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%1 = lshr i32 %0, 4
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%2 = shl nuw i32 %1, 4
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%3 = add i32 %2, -16
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%4 = lshr i32 %3, 4
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%5 = add nuw nsw i32 %4, 1
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br i1 %conflict.rdx, label %for.body.preheader, label %vector.ph
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for.body.preheader: ; preds = %vector.memcheck
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%6 = add i32 %N, -1
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%xtraiter = and i32 %N, 3
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%7 = icmp ult i32 %6, 3
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%8 = add i32 %N, -4
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%9 = sub i32 %8, %xtraiter
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%10 = lshr i32 %9, 2
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%11 = add nuw nsw i32 %10, 1
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br i1 %7, label %for.cond.cleanup.loopexit.unr-lcssa, label %for.body.preheader.new
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for.body.preheader.new: ; preds = %for.body.preheader
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call void @llvm.set.loop.iterations.i32(i32 %11)
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br label %for.body
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vector.ph: ; preds = %vector.memcheck
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call void @llvm.set.loop.iterations.i32(i32 %5)
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br label %vector.body
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vector.body: ; preds = %vector.body, %vector.ph
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%lsr.iv50 = phi i8* [ %scevgep51, %vector.body ], [ %res, %vector.ph ]
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%lsr.iv47 = phi i8* [ %scevgep48, %vector.body ], [ %b, %vector.ph ]
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%lsr.iv = phi i8* [ %scevgep45, %vector.body ], [ %a, %vector.ph ]
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%12 = phi i32 [ %5, %vector.ph ], [ %17, %vector.body ]
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%13 = phi i32 [ %N, %vector.ph ], [ %15, %vector.body ]
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%lsr.iv5052 = bitcast i8* %lsr.iv50 to <16 x i8>*
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%lsr.iv4749 = bitcast i8* %lsr.iv47 to <16 x i8>*
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%lsr.iv46 = bitcast i8* %lsr.iv to <16 x i8>*
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%14 = call <16 x i1> @llvm.arm.mve.vctp8(i32 %13)
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%15 = sub i32 %13, 16
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%wide.masked.load = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv46, i32 1, <16 x i1> %14, <16 x i8> undef)
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%wide.masked.load19 = call <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>* %lsr.iv4749, i32 1, <16 x i1> %14, <16 x i8> undef)
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%16 = add <16 x i8> %wide.masked.load19, %wide.masked.load
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call void @llvm.masked.store.v16i8.p0v16i8(<16 x i8> %16, <16 x i8>* %lsr.iv5052, i32 1, <16 x i1> %14)
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%scevgep45 = getelementptr i8, i8* %lsr.iv, i32 16
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%scevgep48 = getelementptr i8, i8* %lsr.iv47, i32 16
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%scevgep51 = getelementptr i8, i8* %lsr.iv50, i32 16
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%17 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1)
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%18 = icmp ne i32 %17, 0
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br i1 %18, label %vector.body, label %for.cond.cleanup
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for.cond.cleanup.loopexit.unr-lcssa: ; preds = %for.body, %for.body.preheader
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%i.011.unr = phi i32 [ 0, %for.body.preheader ], [ %inc.3, %for.body ]
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%lcmp.mod = icmp eq i32 %xtraiter, 0
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br i1 %lcmp.mod, label %for.cond.cleanup, label %for.body.epil
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for.body.epil: ; preds = %for.cond.cleanup.loopexit.unr-lcssa
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%arrayidx.epil = getelementptr inbounds i8, i8* %a, i32 %i.011.unr
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%19 = load i8, i8* %arrayidx.epil, align 1
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%arrayidx1.epil = getelementptr inbounds i8, i8* %b, i32 %i.011.unr
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%20 = load i8, i8* %arrayidx1.epil, align 1
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%add.epil = add i8 %20, %19
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%arrayidx4.epil = getelementptr inbounds i8, i8* %res, i32 %i.011.unr
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store i8 %add.epil, i8* %arrayidx4.epil, align 1
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%inc.epil = add nuw i32 %i.011.unr, 1
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%epil.iter.cmp = icmp eq i32 %xtraiter, 1
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br i1 %epil.iter.cmp, label %for.cond.cleanup, label %for.body.epil.1
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for.cond.cleanup: ; preds = %vector.body, %for.cond.cleanup.loopexit.unr-lcssa, %for.body.epil.1, %for.body.epil, %for.body.epil.2, %entry
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ret void
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for.body: ; preds = %for.body, %for.body.preheader.new
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%i.011 = phi i32 [ 0, %for.body.preheader.new ], [ %inc.3, %for.body ]
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%21 = phi i32 [ %11, %for.body.preheader.new ], [ %30, %for.body ]
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%scevgep23 = getelementptr i8, i8* %a, i32 %i.011
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%scevgep2453 = bitcast i8* %scevgep23 to i8*
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%22 = load i8, i8* %scevgep2453, align 1
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%scevgep27 = getelementptr i8, i8* %b, i32 %i.011
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%scevgep2854 = bitcast i8* %scevgep27 to i8*
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%23 = load i8, i8* %scevgep2854, align 1
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%add = add i8 %23, %22
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%scevgep31 = getelementptr i8, i8* %res, i32 %i.011
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%scevgep3255 = bitcast i8* %scevgep31 to i8*
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store i8 %add, i8* %scevgep3255, align 1
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%scevgep39 = getelementptr i8, i8* %a, i32 %i.011
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%scevgep40 = getelementptr i8, i8* %scevgep39, i32 1
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%24 = load i8, i8* %scevgep40, align 1
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%scevgep41 = getelementptr i8, i8* %b, i32 %i.011
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%scevgep42 = getelementptr i8, i8* %scevgep41, i32 1
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%25 = load i8, i8* %scevgep42, align 1
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%add.1 = add i8 %25, %24
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%scevgep43 = getelementptr i8, i8* %res, i32 %i.011
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%scevgep44 = getelementptr i8, i8* %scevgep43, i32 1
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store i8 %add.1, i8* %scevgep44, align 1
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%scevgep33 = getelementptr i8, i8* %a, i32 %i.011
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%scevgep34 = getelementptr i8, i8* %scevgep33, i32 2
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%26 = load i8, i8* %scevgep34, align 1
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%scevgep35 = getelementptr i8, i8* %b, i32 %i.011
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%scevgep36 = getelementptr i8, i8* %scevgep35, i32 2
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%27 = load i8, i8* %scevgep36, align 1
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%add.2 = add i8 %27, %26
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%scevgep37 = getelementptr i8, i8* %res, i32 %i.011
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%scevgep38 = getelementptr i8, i8* %scevgep37, i32 2
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store i8 %add.2, i8* %scevgep38, align 1
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%scevgep21 = getelementptr i8, i8* %a, i32 %i.011
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%scevgep22 = getelementptr i8, i8* %scevgep21, i32 3
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%28 = load i8, i8* %scevgep22, align 1
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%scevgep25 = getelementptr i8, i8* %b, i32 %i.011
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%scevgep26 = getelementptr i8, i8* %scevgep25, i32 3
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%29 = load i8, i8* %scevgep26, align 1
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%add.3 = add i8 %29, %28
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%scevgep29 = getelementptr i8, i8* %res, i32 %i.011
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%scevgep30 = getelementptr i8, i8* %scevgep29, i32 3
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store i8 %add.3, i8* %scevgep30, align 1
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%inc.3 = add nuw i32 %i.011, 4
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%30 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %21, i32 1)
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%31 = icmp ne i32 %30, 0
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br i1 %31, label %for.body, label %for.cond.cleanup.loopexit.unr-lcssa
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for.body.epil.1: ; preds = %for.body.epil
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%arrayidx.epil.1 = getelementptr inbounds i8, i8* %a, i32 %inc.epil
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%32 = load i8, i8* %arrayidx.epil.1, align 1
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%arrayidx1.epil.1 = getelementptr inbounds i8, i8* %b, i32 %inc.epil
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%33 = load i8, i8* %arrayidx1.epil.1, align 1
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%add.epil.1 = add i8 %33, %32
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%arrayidx4.epil.1 = getelementptr inbounds i8, i8* %res, i32 %inc.epil
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store i8 %add.epil.1, i8* %arrayidx4.epil.1, align 1
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%inc.epil.1 = add nuw i32 %i.011.unr, 2
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%epil.iter.cmp.1 = icmp eq i32 %xtraiter, 2
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br i1 %epil.iter.cmp.1, label %for.cond.cleanup, label %for.body.epil.2
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for.body.epil.2: ; preds = %for.body.epil.1
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%arrayidx.epil.2 = getelementptr inbounds i8, i8* %a, i32 %inc.epil.1
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%34 = load i8, i8* %arrayidx.epil.2, align 1
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%arrayidx1.epil.2 = getelementptr inbounds i8, i8* %b, i32 %inc.epil.1
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%35 = load i8, i8* %arrayidx1.epil.2, align 1
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%add.epil.2 = add i8 %35, %34
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%arrayidx4.epil.2 = getelementptr inbounds i8, i8* %res, i32 %inc.epil.1
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store i8 %add.epil.2, i8* %arrayidx4.epil.2, align 1
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br label %for.cond.cleanup
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}
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declare <16 x i8> @llvm.masked.load.v16i8.p0v16i8(<16 x i8>*, i32 immarg, <16 x i1>, <16 x i8>) #1
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declare void @llvm.masked.store.v16i8.p0v16i8(<16 x i8>, <16 x i8>*, i32 immarg, <16 x i1>) #2
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declare void @llvm.set.loop.iterations.i32(i32) #3
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declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
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declare <16 x i1> @llvm.arm.mve.vctp8(i32) #4
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...
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---
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name: unrolled_and_vector
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins:
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- { reg: '$r0', virtual-reg: '' }
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- { reg: '$r1', virtual-reg: '' }
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- { reg: '$r2', virtual-reg: '' }
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- { reg: '$r3', virtual-reg: '' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 32
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offsetAdjustment: -24
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack:
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- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r11', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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- { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
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stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
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debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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; CHECK-LABEL: name: unrolled_and_vector
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; CHECK: bb.0.entry:
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; CHECK: successors: %bb.11(0x30000000), %bb.1(0x50000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r8, $r9, $r11
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; CHECK: frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 20
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; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
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; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
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; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -12
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; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -16
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; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -20
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; CHECK: dead $r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
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; CHECK: frame-setup CFI_INSTRUCTION def_cfa $r7, 8
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; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r11
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; CHECK: frame-setup CFI_INSTRUCTION offset $r11, -24
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; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -28
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; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -32
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; CHECK: tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
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; CHECK: tBcc %bb.11, 0, killed $cpsr
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; CHECK: bb.1.vector.memcheck:
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; CHECK: successors: %bb.2(0x40000000), %bb.4(0x40000000)
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; CHECK: liveins: $r0, $r1, $r2, $r3
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; CHECK: renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
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; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
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; CHECK: tCMPr renamable $r4, renamable $r2, 14, $noreg, implicit-def $cpsr
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; CHECK: renamable $lr = t2MOVi 1, 14, $noreg, $noreg
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; CHECK: renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
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; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
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; CHECK: renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
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; CHECK: tCMPr killed renamable $r4, renamable $r1, 14, $noreg, implicit-def $cpsr
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; CHECK: renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
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; CHECK: renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
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; CHECK: tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
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; CHECK: renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
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; CHECK: renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg
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; CHECK: dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg
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; CHECK: t2IT 0, 4, implicit-def $itstate
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; CHECK: renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit killed $r6, implicit $itstate
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; CHECK: dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
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; CHECK: tBcc %bb.4, 0, killed $cpsr
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; CHECK: bb.2.for.body.preheader:
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; CHECK: successors: %bb.3(0x40000000), %bb.6(0x40000000)
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; CHECK: liveins: $lr, $r0, $r1, $r2, $r3
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; CHECK: renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg
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; CHECK: renamable $r12 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg
|
||||
; CHECK: tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.6, 2, killed $cpsr
|
||||
; CHECK: bb.3:
|
||||
; CHECK: successors: %bb.8(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r12
|
||||
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
; CHECK: tB %bb.8, 14, $noreg
|
||||
; CHECK: bb.4.vector.ph:
|
||||
; CHECK: successors: %bb.5(0x80000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3
|
||||
; CHECK: $lr = MVE_DLSTP_8 killed renamable $r3
|
||||
; CHECK: bb.5.vector.body:
|
||||
; CHECK: successors: %bb.5(0x7c000000), %bb.11(0x04000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2
|
||||
; CHECK: renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 0, $noreg :: (load 16 from %ir.lsr.iv46, align 1)
|
||||
; CHECK: renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 0, $noreg :: (load 16 from %ir.lsr.iv4749, align 1)
|
||||
; CHECK: renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
|
||||
; CHECK: renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 0, killed $noreg :: (store 16 into %ir.lsr.iv5052, align 1)
|
||||
; CHECK: $lr = MVE_LETP killed renamable $lr, %bb.5
|
||||
; CHECK: tB %bb.11, 14, $noreg
|
||||
; CHECK: bb.6.for.body.preheader.new:
|
||||
; CHECK: successors: %bb.7(0x80000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
|
||||
; CHECK: renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
|
||||
; CHECK: renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
|
||||
; CHECK: renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14, $noreg, $noreg
|
||||
; CHECK: renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
; CHECK: $lr = t2DLS killed renamable $lr
|
||||
; CHECK: bb.7.for.body:
|
||||
; CHECK: successors: %bb.7(0x7c000000), %bb.8(0x04000000)
|
||||
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r12
|
||||
; CHECK: renamable $r4 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.scevgep2453)
|
||||
; CHECK: renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
|
||||
; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.scevgep2854)
|
||||
; CHECK: renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
|
||||
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14, $noreg
|
||||
; CHECK: tSTRBr killed renamable $r4, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.scevgep3255)
|
||||
; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 1, 14, $noreg :: (load 1 from %ir.scevgep40)
|
||||
; CHECK: renamable $r5 = tLDRBi renamable $r6, 1, 14, $noreg :: (load 1 from %ir.scevgep42)
|
||||
; CHECK: renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14, $noreg
|
||||
; CHECK: renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
|
||||
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg
|
||||
; CHECK: t2STRBi12 killed renamable $r8, renamable $r5, 1, 14, $noreg :: (store 1 into %ir.scevgep44)
|
||||
; CHECK: renamable $r8 = t2LDRBi12 renamable $r9, 2, 14, $noreg :: (load 1 from %ir.scevgep34)
|
||||
; CHECK: renamable $r4 = tLDRBi renamable $r6, 2, 14, $noreg :: (load 1 from %ir.scevgep36)
|
||||
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14, $noreg
|
||||
; CHECK: tSTRBi killed renamable $r4, renamable $r5, 2, 14, $noreg :: (store 1 into %ir.scevgep38)
|
||||
; CHECK: renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14, $noreg :: (load 1 from %ir.scevgep22)
|
||||
; CHECK: renamable $r6 = tLDRBi killed renamable $r6, 3, 14, $noreg :: (load 1 from %ir.scevgep26)
|
||||
; CHECK: renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14, $noreg
|
||||
; CHECK: tSTRBi killed renamable $r4, killed renamable $r5, 3, 14, $noreg :: (store 1 into %ir.scevgep30)
|
||||
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.7
|
||||
; CHECK: bb.8.for.cond.cleanup.loopexit.unr-lcssa:
|
||||
; CHECK: successors: %bb.11(0x30000000), %bb.9(0x50000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
|
||||
; CHECK: t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: tBcc %bb.11, 0, killed $cpsr
|
||||
; CHECK: bb.9.for.body.epil:
|
||||
; CHECK: successors: %bb.11(0x40000000), %bb.10(0x40000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
|
||||
; CHECK: renamable $r6 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil)
|
||||
; CHECK: t2CMPri renamable $r12, 1, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil)
|
||||
; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14, $noreg
|
||||
; CHECK: tSTRBr killed renamable $r6, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil)
|
||||
; CHECK: tBcc %bb.11, 0, killed $cpsr
|
||||
; CHECK: bb.10.for.body.epil.1:
|
||||
; CHECK: successors: %bb.11(0x40000000), %bb.12(0x40000000)
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3, $r12
|
||||
; CHECK: renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14, $noreg
|
||||
; CHECK: t2CMPri killed renamable $r12, 2, 14, $noreg, implicit-def $cpsr
|
||||
; CHECK: renamable $r5 = tLDRBr renamable $r1, $r6, 14, $noreg :: (load 1 from %ir.arrayidx.epil.1)
|
||||
; CHECK: renamable $r4 = tLDRBr renamable $r2, $r6, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.1)
|
||||
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14, $noreg
|
||||
; CHECK: tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.1)
|
||||
; CHECK: tBcc %bb.12, 1, killed $cpsr
|
||||
; CHECK: bb.11.for.cond.cleanup:
|
||||
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
|
||||
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
; CHECK: bb.12.for.body.epil.2:
|
||||
; CHECK: liveins: $r0, $r1, $r2, $r3
|
||||
; CHECK: renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14, $noreg
|
||||
; CHECK: renamable $r1 = tLDRBr killed renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil.2)
|
||||
; CHECK: renamable $r2 = tLDRBr killed renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.2)
|
||||
; CHECK: renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg
|
||||
; CHECK: tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.2)
|
||||
; CHECK: $sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
|
||||
; CHECK: tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
bb.0.entry:
|
||||
successors: %bb.11(0x30000000), %bb.1(0x50000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $lr, $r8, $r9, $r11
|
||||
|
||||
frame-setup tPUSH 14, $noreg, killed $r4, killed $r5, killed $r6, killed $lr, implicit-def $sp, implicit $sp
|
||||
frame-setup CFI_INSTRUCTION def_cfa_offset 20
|
||||
frame-setup CFI_INSTRUCTION offset $lr, -4
|
||||
frame-setup CFI_INSTRUCTION offset $r7, -8
|
||||
frame-setup CFI_INSTRUCTION offset $r6, -12
|
||||
frame-setup CFI_INSTRUCTION offset $r5, -16
|
||||
frame-setup CFI_INSTRUCTION offset $r4, -20
|
||||
$r7 = frame-setup tADDrSPi $sp, 3, 14, $noreg
|
||||
frame-setup CFI_INSTRUCTION def_cfa $r7, 8
|
||||
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r8, killed $r9, killed $r11
|
||||
frame-setup CFI_INSTRUCTION offset $r11, -24
|
||||
frame-setup CFI_INSTRUCTION offset $r9, -28
|
||||
frame-setup CFI_INSTRUCTION offset $r8, -32
|
||||
tCMPi8 renamable $r3, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.11, 0, killed $cpsr
|
||||
|
||||
bb.1.vector.memcheck:
|
||||
successors: %bb.2(0x40000000), %bb.4(0x40000000)
|
||||
liveins: $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $r4, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
|
||||
renamable $r5, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
|
||||
tCMPr renamable $r4, renamable $r2, 14, $noreg, implicit-def $cpsr
|
||||
renamable $lr = t2MOVi 1, 14, $noreg, $noreg
|
||||
renamable $r12 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
|
||||
tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
|
||||
renamable $r6 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
|
||||
tCMPr killed renamable $r4, renamable $r1, 14, $noreg, implicit-def $cpsr
|
||||
renamable $r5 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
|
||||
renamable $r4 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
|
||||
tCMPr killed renamable $r5, renamable $r0, 14, $noreg, implicit-def $cpsr
|
||||
renamable $r5 = t2CSINC $zr, $zr, 9, implicit killed $cpsr
|
||||
renamable $r5, dead $cpsr = tAND killed renamable $r5, killed renamable $r4, 14, $noreg
|
||||
dead renamable $r5, $cpsr = tLSLri killed renamable $r5, 31, 14, $noreg
|
||||
t2IT 0, 4, implicit-def $itstate
|
||||
renamable $r6 = t2ANDrr killed renamable $r6, killed renamable $r12, 0, $cpsr, $noreg, implicit $r6, implicit $itstate
|
||||
dead renamable $r6 = t2LSLri killed renamable $r6, 31, 0, killed $cpsr, def $cpsr, implicit killed $r6, implicit killed $itstate
|
||||
tBcc %bb.4, 0, killed $cpsr
|
||||
|
||||
bb.2.for.body.preheader:
|
||||
successors: %bb.3(0x40000000), %bb.6(0x40000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $r4, dead $cpsr = tSUBi3 renamable $r3, 1, 14, $noreg
|
||||
renamable $r12 = t2ANDri renamable $r3, 3, 14, $noreg, $noreg
|
||||
tCMPi8 killed renamable $r4, 3, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.6, 2, killed $cpsr
|
||||
|
||||
bb.3:
|
||||
successors: %bb.8(0x80000000)
|
||||
liveins: $r0, $r1, $r2, $r12
|
||||
|
||||
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
tB %bb.8, 14, $noreg
|
||||
|
||||
bb.4.vector.ph:
|
||||
successors: %bb.5(0x80000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $r6 = t2ADDri renamable $r3, 15, 14, $noreg, $noreg
|
||||
renamable $r6 = t2BICri killed renamable $r6, 15, 14, $noreg, $noreg
|
||||
renamable $r6, dead $cpsr = tSUBi8 killed renamable $r6, 16, 14, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r6, 35, 14, $noreg, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.5.vector.body:
|
||||
successors: %bb.5(0x7c000000), %bb.11(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $vpr = MVE_VCTP8 renamable $r3, 0, $noreg
|
||||
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 16, 14, $noreg
|
||||
MVE_VPST 4, implicit $vpr
|
||||
renamable $r1, renamable $q0 = MVE_VLDRBU8_post killed renamable $r1, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv46, align 1)
|
||||
renamable $r2, renamable $q1 = MVE_VLDRBU8_post killed renamable $r2, 16, 1, renamable $vpr :: (load 16 from %ir.lsr.iv4749, align 1)
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $q0 = MVE_VADDi8 killed renamable $q1, killed renamable $q0, 0, $noreg, undef renamable $q0
|
||||
MVE_VPST 8, implicit $vpr
|
||||
renamable $r0 = MVE_VSTRBU8_post killed renamable $q0, killed renamable $r0, 16, 1, killed renamable $vpr :: (store 16 into %ir.lsr.iv5052, align 1)
|
||||
t2LoopEnd renamable $lr, %bb.5, implicit-def dead $cpsr
|
||||
tB %bb.11, 14, $noreg
|
||||
|
||||
bb.6.for.body.preheader.new:
|
||||
successors: %bb.7(0x80000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
renamable $r3 = t2BICri killed renamable $r3, 3, 14, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tSUBi8 killed renamable $r3, 4, 14, $noreg
|
||||
renamable $lr = nuw nsw t2ADDrs killed renamable $lr, killed renamable $r3, 19, 14, $noreg, $noreg
|
||||
renamable $r3, dead $cpsr = tMOVi8 0, 14, $noreg
|
||||
t2DoLoopStart renamable $lr
|
||||
|
||||
bb.7.for.body:
|
||||
successors: %bb.7(0x7c000000), %bb.8(0x04000000)
|
||||
liveins: $lr, $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
renamable $r4 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.scevgep2453)
|
||||
renamable $r9 = t2ADDrr renamable $r1, renamable $r3, 14, $noreg, $noreg
|
||||
renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.scevgep2854)
|
||||
renamable $r6, dead $cpsr = tADDrr renamable $r2, renamable $r3, 14, $noreg
|
||||
renamable $lr = t2LoopDec killed renamable $lr, 1
|
||||
renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r5, 14, $noreg
|
||||
tSTRBr killed renamable $r4, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.scevgep3255)
|
||||
renamable $r8 = t2LDRBi12 renamable $r9, 1, 14, $noreg :: (load 1 from %ir.scevgep40)
|
||||
renamable $r5 = tLDRBi renamable $r6, 1, 14, $noreg :: (load 1 from %ir.scevgep42)
|
||||
renamable $r8 = tADDhirr killed renamable $r8, killed renamable $r5, 14, $noreg
|
||||
renamable $r5, dead $cpsr = tADDrr renamable $r0, renamable $r3, 14, $noreg
|
||||
renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 4, 14, $noreg
|
||||
t2STRBi12 killed renamable $r8, renamable $r5, 1, 14, $noreg :: (store 1 into %ir.scevgep44)
|
||||
renamable $r8 = t2LDRBi12 renamable $r9, 2, 14, $noreg :: (load 1 from %ir.scevgep34)
|
||||
renamable $r4 = tLDRBi renamable $r6, 2, 14, $noreg :: (load 1 from %ir.scevgep36)
|
||||
renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r8, 14, $noreg
|
||||
tSTRBi killed renamable $r4, renamable $r5, 2, 14, $noreg :: (store 1 into %ir.scevgep38)
|
||||
renamable $r4 = t2LDRBi12 killed renamable $r9, 3, 14, $noreg :: (load 1 from %ir.scevgep22)
|
||||
renamable $r6 = tLDRBi killed renamable $r6, 3, 14, $noreg :: (load 1 from %ir.scevgep26)
|
||||
renamable $r4 = tADDhirr killed renamable $r4, killed renamable $r6, 14, $noreg
|
||||
tSTRBi killed renamable $r4, killed renamable $r5, 3, 14, $noreg :: (store 1 into %ir.scevgep30)
|
||||
t2LoopEnd renamable $lr, %bb.7, implicit-def dead $cpsr
|
||||
tB %bb.8, 14, $noreg
|
||||
|
||||
bb.8.for.cond.cleanup.loopexit.unr-lcssa:
|
||||
successors: %bb.11(0x30000000), %bb.9(0x50000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
t2CMPri renamable $r12, 0, 14, $noreg, implicit-def $cpsr
|
||||
tBcc %bb.11, 0, killed $cpsr
|
||||
|
||||
bb.9.for.body.epil:
|
||||
successors: %bb.11(0x40000000), %bb.10(0x40000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
renamable $r6 = tLDRBr renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil)
|
||||
t2CMPri renamable $r12, 1, 14, $noreg, implicit-def $cpsr
|
||||
renamable $r5 = tLDRBr renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil)
|
||||
renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r5, 14, $noreg
|
||||
tSTRBr killed renamable $r6, renamable $r0, $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil)
|
||||
tBcc %bb.11, 0, killed $cpsr
|
||||
|
||||
bb.10.for.body.epil.1:
|
||||
successors: %bb.11(0x40000000), %bb.12(0x40000000)
|
||||
liveins: $r0, $r1, $r2, $r3, $r12
|
||||
|
||||
renamable $r6, dead $cpsr = nuw tADDi3 renamable $r3, 1, 14, $noreg
|
||||
t2CMPri killed renamable $r12, 2, 14, $noreg, implicit-def $cpsr
|
||||
renamable $r5 = tLDRBr renamable $r1, $r6, 14, $noreg :: (load 1 from %ir.arrayidx.epil.1)
|
||||
renamable $r4 = tLDRBr renamable $r2, $r6, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.1)
|
||||
renamable $r5 = tADDhirr killed renamable $r5, killed renamable $r4, 14, $noreg
|
||||
tSTRBr killed renamable $r5, renamable $r0, killed $r6, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.1)
|
||||
tBcc %bb.12, 1, killed $cpsr
|
||||
|
||||
bb.11.for.cond.cleanup:
|
||||
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
|
||||
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
|
||||
bb.12.for.body.epil.2:
|
||||
liveins: $r0, $r1, $r2, $r3
|
||||
|
||||
renamable $r3, dead $cpsr = nuw tADDi8 killed renamable $r3, 2, 14, $noreg
|
||||
renamable $r1 = tLDRBr killed renamable $r1, $r3, 14, $noreg :: (load 1 from %ir.arrayidx.epil.2)
|
||||
renamable $r2 = tLDRBr killed renamable $r2, $r3, 14, $noreg :: (load 1 from %ir.arrayidx1.epil.2)
|
||||
renamable $r1 = tADDhirr killed renamable $r1, killed renamable $r2, 14, $noreg
|
||||
tSTRBr killed renamable $r1, killed renamable $r0, killed $r3, 14, $noreg :: (store 1 into %ir.arrayidx4.epil.2)
|
||||
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r8, def $r9, def $r11
|
||||
tPOP_RET 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $pc
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue